1From 7c4d9a6a758200f89a4659673dd43162164ddd0c Mon Sep 17 00:00:00 2001
2From: Kevin Zhao <kevin.zhao@linaro.org>
3Date: Thu, 22 Jul 2021 16:00:21 +0800
4Subject: [PATCH] arm64 front end: add support for 'dc cvac', 'dc cvap',
5 handling it the same as 'dc cvau'.
6
7Signed-off-by: Kevin Zhao <kevin.zhao@linaro.org>
8---
9 VEX/priv/guest_arm64_toIR.c | 6 +++++-
10 1 file changed, 5 insertions(+), 1 deletion(-)
11
12diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
13index 12a1c59..44a1c23 100644
14--- a/VEX/priv/guest_arm64_toIR.c
15+++ b/VEX/priv/guest_arm64_toIR.c
16@@ -7467,9 +7467,13 @@ Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres, UInt insn,
17    /* ------------------ DC_CVAU ------------------ */
18    /* D5 0B 7B 001 Rt  dc cvau, rT
19       D5 0B 7E 001 Rt  dc civac, rT
20+      D5 0B 7A 001 Rt  dc cvac, rT
21+      D5 0B 7C 001 Rt  dc cvap, rT
22    */
23    if (   (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7B20
24-       || (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7E20) {
25+       || (INSN(31,0) & 0xFFFFFFE0) == 0xD50B7E20
26+       || ((INSN(31,0) & 0xFFFFFFE0) == 0xD50B7A20)
27+       || ((INSN(31,0) & 0xFFFFFFE0) == 0xD50B7C20)) {
28       /* Exactly the same scheme as for IC IVAU, except we observe the
29          dMinLine size, and request an Ijk_FlushDCache instead of
30          Ijk_InvalICache. */
31--
322.20.1
33
34