1*4882a593Smuzhiyun# mips default CPU ISAs 2*4882a593Smuzhiyunconfig BR2_MIPS_CPU_MIPS32 3*4882a593Smuzhiyun bool 4*4882a593Smuzhiyun select BR2_MIPS_NAN_LEGACY 5*4882a593Smuzhiyunconfig BR2_MIPS_CPU_MIPS32R2 6*4882a593Smuzhiyun bool 7*4882a593Smuzhiyun select BR2_MIPS_NAN_LEGACY 8*4882a593Smuzhiyunconfig BR2_MIPS_CPU_MIPS32R3 9*4882a593Smuzhiyun bool 10*4882a593Smuzhiyun select BR2_MIPS_NAN_LEGACY 11*4882a593Smuzhiyunconfig BR2_MIPS_CPU_MIPS32R5 12*4882a593Smuzhiyun bool 13*4882a593Smuzhiyun select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 14*4882a593Smuzhiyunconfig BR2_MIPS_CPU_MIPS32R6 15*4882a593Smuzhiyun bool 16*4882a593Smuzhiyun select BR2_MIPS_NAN_2008 17*4882a593Smuzhiyun select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 18*4882a593Smuzhiyunconfig BR2_MIPS_CPU_MIPS64 19*4882a593Smuzhiyun bool 20*4882a593Smuzhiyun select BR2_MIPS_NAN_LEGACY 21*4882a593Smuzhiyunconfig BR2_MIPS_CPU_MIPS64R2 22*4882a593Smuzhiyun bool 23*4882a593Smuzhiyun select BR2_MIPS_NAN_LEGACY 24*4882a593Smuzhiyunconfig BR2_MIPS_CPU_MIPS64R3 25*4882a593Smuzhiyun bool 26*4882a593Smuzhiyun select BR2_MIPS_NAN_LEGACY 27*4882a593Smuzhiyunconfig BR2_MIPS_CPU_MIPS64R5 28*4882a593Smuzhiyun bool 29*4882a593Smuzhiyun select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 30*4882a593Smuzhiyunconfig BR2_MIPS_CPU_MIPS64R6 31*4882a593Smuzhiyun bool 32*4882a593Smuzhiyun select BR2_MIPS_NAN_2008 33*4882a593Smuzhiyun select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunchoice 36*4882a593Smuzhiyun prompt "Target Architecture Variant" 37*4882a593Smuzhiyun default BR2_mips_32 if BR2_mips || BR2_mipsel 38*4882a593Smuzhiyun default BR2_mips_64 if BR2_mips64 || BR2_mips64el 39*4882a593Smuzhiyun depends on BR2_mips || BR2_mipsel || BR2_mips64 || BR2_mips64el 40*4882a593Smuzhiyun help 41*4882a593Smuzhiyun Specific CPU variant to use 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun 64bit capable: 64, 64r2, 64r3, 64r5, 64r6 44*4882a593Smuzhiyun non-64bit capable: 32, 32r2, 32r3, 32r5, 32r6 45*4882a593Smuzhiyun 46*4882a593Smuzhiyunconfig BR2_mips_32 47*4882a593Smuzhiyun bool "Generic MIPS32" 48*4882a593Smuzhiyun depends on !BR2_ARCH_IS_64 49*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS32 50*4882a593Smuzhiyunconfig BR2_mips_32r2 51*4882a593Smuzhiyun bool "Generic MIPS32R2" 52*4882a593Smuzhiyun depends on !BR2_ARCH_IS_64 53*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS32R2 54*4882a593Smuzhiyunconfig BR2_mips_32r3 55*4882a593Smuzhiyun bool "Generic MIPS32R3" 56*4882a593Smuzhiyun depends on !BR2_ARCH_IS_64 57*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS32R3 58*4882a593Smuzhiyunconfig BR2_mips_32r5 59*4882a593Smuzhiyun bool "Generic MIPS32R5" 60*4882a593Smuzhiyun depends on !BR2_ARCH_IS_64 61*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS32R5 62*4882a593Smuzhiyunconfig BR2_mips_32r6 63*4882a593Smuzhiyun bool "Generic MIPS32R6" 64*4882a593Smuzhiyun depends on !BR2_ARCH_IS_64 65*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS32R6 66*4882a593Smuzhiyunconfig BR2_mips_interaptiv 67*4882a593Smuzhiyun bool "interAptiv" 68*4882a593Smuzhiyun depends on !BR2_ARCH_IS_64 69*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS32R2 70*4882a593Smuzhiyun select BR2_ARCH_NEEDS_GCC_AT_LEAST_6 71*4882a593Smuzhiyunconfig BR2_mips_m5150 72*4882a593Smuzhiyun bool "M5150" 73*4882a593Smuzhiyun depends on !BR2_ARCH_IS_64 74*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS32R5 75*4882a593Smuzhiyun select BR2_MIPS_NAN_2008 76*4882a593Smuzhiyun select BR2_ARCH_NEEDS_GCC_AT_LEAST_6 77*4882a593Smuzhiyunconfig BR2_mips_m6250 78*4882a593Smuzhiyun bool "M6250" 79*4882a593Smuzhiyun depends on !BR2_ARCH_IS_64 80*4882a593Smuzhiyun select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT 81*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS32R6 82*4882a593Smuzhiyunconfig BR2_mips_p5600 83*4882a593Smuzhiyun bool "P5600" 84*4882a593Smuzhiyun depends on !BR2_ARCH_IS_64 85*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS32R5 86*4882a593Smuzhiyun select BR2_MIPS_NAN_2008 87*4882a593Smuzhiyunconfig BR2_mips_xburst 88*4882a593Smuzhiyun bool "XBurst" 89*4882a593Smuzhiyun depends on !BR2_ARCH_IS_64 90*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS32R2 91*4882a593Smuzhiyun help 92*4882a593Smuzhiyun The Ingenic XBurst is a MIPS32R2 microprocessor. It has a 93*4882a593Smuzhiyun bug in the FPU that can generate incorrect results in 94*4882a593Smuzhiyun certain cases. The problem shows up when you have several 95*4882a593Smuzhiyun fused madd instructions in sequence with dependant 96*4882a593Smuzhiyun operands. This requires the -mno-fused-madd compiler option 97*4882a593Smuzhiyun to be used in order to prevent emitting these instructions. 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun See http://www.ingenic.com/en/?xburst.html 100*4882a593Smuzhiyunconfig BR2_mips_64 101*4882a593Smuzhiyun bool "Generic MIPS64" 102*4882a593Smuzhiyun depends on BR2_ARCH_IS_64 103*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS64 104*4882a593Smuzhiyunconfig BR2_mips_64r2 105*4882a593Smuzhiyun bool "Generic MIPS64R2" 106*4882a593Smuzhiyun depends on BR2_ARCH_IS_64 107*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS64R2 108*4882a593Smuzhiyunconfig BR2_mips_64r3 109*4882a593Smuzhiyun bool "Generic MIPS64R3" 110*4882a593Smuzhiyun depends on BR2_ARCH_IS_64 111*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS64R3 112*4882a593Smuzhiyunconfig BR2_mips_64r5 113*4882a593Smuzhiyun bool "Generic MIPS64R5" 114*4882a593Smuzhiyun depends on BR2_ARCH_IS_64 115*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS64R5 116*4882a593Smuzhiyunconfig BR2_mips_64r6 117*4882a593Smuzhiyun bool "Generic MIPS64R6" 118*4882a593Smuzhiyun depends on BR2_ARCH_IS_64 119*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS64R6 120*4882a593Smuzhiyunconfig BR2_mips_i6400 121*4882a593Smuzhiyun bool "I6400" 122*4882a593Smuzhiyun depends on BR2_ARCH_IS_64 123*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS64R6 124*4882a593Smuzhiyun select BR2_ARCH_NEEDS_GCC_AT_LEAST_6 125*4882a593Smuzhiyunconfig BR2_mips_octeon2 126*4882a593Smuzhiyun bool "Octeon II" 127*4882a593Smuzhiyun depends on BR2_ARCH_IS_64 128*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS64R2 129*4882a593Smuzhiyun help 130*4882a593Smuzhiyun Marvell (formerly Cavium Networks) Octeon II CN60XX 131*4882a593Smuzhiyun processors. 132*4882a593Smuzhiyunconfig BR2_mips_octeon3 133*4882a593Smuzhiyun bool "Octeon III" 134*4882a593Smuzhiyun depends on BR2_ARCH_IS_64 135*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS64R3 136*4882a593Smuzhiyun help 137*4882a593Smuzhiyun Marvell (formerly Cavium Networks) Octeon III CN7XXX 138*4882a593Smuzhiyun processors. 139*4882a593Smuzhiyunconfig BR2_mips_p6600 140*4882a593Smuzhiyun bool "P6600" 141*4882a593Smuzhiyun depends on BR2_ARCH_IS_64 142*4882a593Smuzhiyun select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT 143*4882a593Smuzhiyun select BR2_MIPS_CPU_MIPS64R6 144*4882a593Smuzhiyunendchoice 145*4882a593Smuzhiyun 146*4882a593Smuzhiyunchoice 147*4882a593Smuzhiyun prompt "Target ABI" 148*4882a593Smuzhiyun default BR2_MIPS_NABI32 149*4882a593Smuzhiyun depends on BR2_mips64 || BR2_mips64el 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun help 152*4882a593Smuzhiyun Application Binary Interface to use 153*4882a593Smuzhiyun 154*4882a593Smuzhiyunconfig BR2_MIPS_NABI32 155*4882a593Smuzhiyun bool "n32" 156*4882a593Smuzhiyun depends on BR2_ARCH_IS_64 157*4882a593Smuzhiyun select BR2_KERNEL_64_USERLAND_32 158*4882a593Smuzhiyunconfig BR2_MIPS_NABI64 159*4882a593Smuzhiyun bool "n64" 160*4882a593Smuzhiyun depends on BR2_ARCH_IS_64 161*4882a593Smuzhiyunendchoice 162*4882a593Smuzhiyun 163*4882a593Smuzhiyunconfig BR2_MIPS_SOFT_FLOAT 164*4882a593Smuzhiyun bool "Use soft-float" 165*4882a593Smuzhiyun default y 166*4882a593Smuzhiyun depends on !BR2_mips_octeon3 # hard-float only 167*4882a593Smuzhiyun select BR2_SOFT_FLOAT 168*4882a593Smuzhiyun help 169*4882a593Smuzhiyun If your target CPU does not have a Floating Point Unit (FPU) 170*4882a593Smuzhiyun or a kernel FPU emulator, but you still wish to support 171*4882a593Smuzhiyun floating point functions, then everything will need to be 172*4882a593Smuzhiyun compiled with soft floating point support (-msoft-float). 173*4882a593Smuzhiyun 174*4882a593Smuzhiyunchoice 175*4882a593Smuzhiyun prompt "FP mode" 176*4882a593Smuzhiyun default BR2_MIPS_FP32_MODE_XX 177*4882a593Smuzhiyun depends on !BR2_ARCH_IS_64 && !BR2_MIPS_SOFT_FLOAT 178*4882a593Smuzhiyun help 179*4882a593Smuzhiyun MIPS32 supports different FP modes (32,xx,64). Information 180*4882a593Smuzhiyun about FP modes can be found here: 181*4882a593Smuzhiyun https://sourceware.org/binutils/docs/as/MIPS-Options.html 182*4882a593Smuzhiyun https://dmz-portal.imgtec.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking#5._Generating_modeless_code 183*4882a593Smuzhiyun 184*4882a593Smuzhiyunconfig BR2_MIPS_FP32_MODE_32 185*4882a593Smuzhiyun bool "32" 186*4882a593Smuzhiyun depends on !BR2_MIPS_CPU_MIPS32R6 187*4882a593Smuzhiyun 188*4882a593Smuzhiyunconfig BR2_MIPS_FP32_MODE_XX 189*4882a593Smuzhiyun bool "xx" 190*4882a593Smuzhiyun select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 191*4882a593Smuzhiyun 192*4882a593Smuzhiyunconfig BR2_MIPS_FP32_MODE_64 193*4882a593Smuzhiyun bool "64" 194*4882a593Smuzhiyun depends on !BR2_MIPS_CPU_MIPS32 195*4882a593Smuzhiyunendchoice 196*4882a593Smuzhiyun 197*4882a593Smuzhiyunconfig BR2_GCC_TARGET_FP32_MODE 198*4882a593Smuzhiyun default "32" if BR2_MIPS_FP32_MODE_32 199*4882a593Smuzhiyun default "xx" if BR2_MIPS_FP32_MODE_XX 200*4882a593Smuzhiyun default "64" if BR2_MIPS_FP32_MODE_64 201*4882a593Smuzhiyun 202*4882a593Smuzhiyunconfig BR2_MIPS_NAN_LEGACY 203*4882a593Smuzhiyun bool 204*4882a593Smuzhiyun 205*4882a593Smuzhiyunconfig BR2_MIPS_NAN_2008 206*4882a593Smuzhiyun bool 207*4882a593Smuzhiyun select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9 208*4882a593Smuzhiyun 209*4882a593Smuzhiyunchoice 210*4882a593Smuzhiyun prompt "Target NaN" 211*4882a593Smuzhiyun default BR2_MIPS_ENABLE_NAN_2008 212*4882a593Smuzhiyun depends on BR2_mips_32r5 || BR2_mips_64r5 213*4882a593Smuzhiyun help 214*4882a593Smuzhiyun MIPS supports two different NaN encodings, legacy and 2008. 215*4882a593Smuzhiyun Information about MIPS NaN encodings can be found here: 216*4882a593Smuzhiyun https://sourceware.org/binutils/docs/as/MIPS-NaN-Encodings.html 217*4882a593Smuzhiyun 218*4882a593Smuzhiyunconfig BR2_MIPS_ENABLE_NAN_LEGACY 219*4882a593Smuzhiyun bool "legacy" 220*4882a593Smuzhiyun select BR2_MIPS_NAN_LEGACY 221*4882a593Smuzhiyun 222*4882a593Smuzhiyunconfig BR2_MIPS_ENABLE_NAN_2008 223*4882a593Smuzhiyun bool "2008" 224*4882a593Smuzhiyun depends on !BR2_MIPS_SOFT_FLOAT 225*4882a593Smuzhiyun select BR2_MIPS_NAN_2008 226*4882a593Smuzhiyunendchoice 227*4882a593Smuzhiyun 228*4882a593Smuzhiyunconfig BR2_GCC_TARGET_NAN 229*4882a593Smuzhiyun default "legacy" if BR2_MIPS_NAN_LEGACY 230*4882a593Smuzhiyun default "2008" if BR2_MIPS_NAN_2008 231*4882a593Smuzhiyun 232*4882a593Smuzhiyunconfig BR2_ARCH 233*4882a593Smuzhiyun default "mips" if BR2_mips 234*4882a593Smuzhiyun default "mipsel" if BR2_mipsel 235*4882a593Smuzhiyun default "mips64" if BR2_mips64 236*4882a593Smuzhiyun default "mips64el" if BR2_mips64el 237*4882a593Smuzhiyun 238*4882a593Smuzhiyunconfig BR2_NORMALIZED_ARCH 239*4882a593Smuzhiyun default "mips" 240*4882a593Smuzhiyun 241*4882a593Smuzhiyunconfig BR2_ENDIAN 242*4882a593Smuzhiyun default "LITTLE" if BR2_mipsel || BR2_mips64el 243*4882a593Smuzhiyun default "BIG" if BR2_mips || BR2_mips64 244*4882a593Smuzhiyun 245*4882a593Smuzhiyunconfig BR2_GCC_TARGET_ARCH 246*4882a593Smuzhiyun default "mips32" if BR2_mips_32 247*4882a593Smuzhiyun default "mips32r2" if BR2_mips_32r2 248*4882a593Smuzhiyun default "mips32r3" if BR2_mips_32r3 249*4882a593Smuzhiyun default "mips32r5" if BR2_mips_32r5 250*4882a593Smuzhiyun default "mips32r6" if BR2_mips_32r6 251*4882a593Smuzhiyun default "interaptiv" if BR2_mips_interaptiv 252*4882a593Smuzhiyun default "m5101" if BR2_mips_m5150 253*4882a593Smuzhiyun default "m6201" if BR2_mips_m6250 254*4882a593Smuzhiyun default "p5600" if BR2_mips_p5600 255*4882a593Smuzhiyun default "mips32r2" if BR2_mips_xburst 256*4882a593Smuzhiyun default "mips64" if BR2_mips_64 257*4882a593Smuzhiyun default "mips64r2" if BR2_mips_64r2 258*4882a593Smuzhiyun default "mips64r3" if BR2_mips_64r3 259*4882a593Smuzhiyun default "mips64r5" if BR2_mips_64r5 260*4882a593Smuzhiyun default "mips64r6" if BR2_mips_64r6 261*4882a593Smuzhiyun default "i6400" if BR2_mips_i6400 262*4882a593Smuzhiyun default "octeon2" if BR2_mips_octeon2 263*4882a593Smuzhiyun default "octeon3" if BR2_mips_octeon3 264*4882a593Smuzhiyun default "p6600" if BR2_mips_p6600 265*4882a593Smuzhiyun 266*4882a593Smuzhiyunconfig BR2_MIPS_OABI32 267*4882a593Smuzhiyun bool 268*4882a593Smuzhiyun default y if BR2_mips || BR2_mipsel 269*4882a593Smuzhiyun 270*4882a593Smuzhiyunconfig BR2_GCC_TARGET_ABI 271*4882a593Smuzhiyun default "32" if BR2_MIPS_OABI32 272*4882a593Smuzhiyun default "n32" if BR2_MIPS_NABI32 273*4882a593Smuzhiyun default "64" if BR2_MIPS_NABI64 274*4882a593Smuzhiyun 275*4882a593Smuzhiyunconfig BR2_READELF_ARCH_NAME 276*4882a593Smuzhiyun default "MIPS R3000" 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun# vim: ft=kconfig 279*4882a593Smuzhiyun# -*- mode:kconfig; -*- 280