Home
last modified time | relevance | path

Searched refs:clk (Results 1 – 14 of 14) sorted by relevance

/utopia/UTPA2-700.0.x/modules/sc/hal/k6/sc/
H A DhalSC.c792 MS_U32 clk; in HAL_SC_SetUartDiv() local
803 clk = 108000000; in HAL_SC_SetUartDiv()
807 clk = 123000000; in HAL_SC_SetUartDiv()
811 clk = 144000000; in HAL_SC_SetUartDiv()
815 clk = 160000000; in HAL_SC_SetUartDiv()
819 clk = 170000000; in HAL_SC_SetUartDiv()
833 clk = 108000000; in HAL_SC_SetUartDiv()
837 clk = 123000000; in HAL_SC_SetUartDiv()
841 clk = 144000000; in HAL_SC_SetUartDiv()
845 clk = 160000000; in HAL_SC_SetUartDiv()
[all …]
/utopia/UTPA2-700.0.x/modules/sc/hal/k6lite/sc/
H A DhalSC.c840 MS_U32 clk; in HAL_SC_SetUartDiv() local
845 clk = _HAL_SC_GetTopClkNum(u8SCID); in HAL_SC_SetUartDiv()
846 if (clk == 0) in HAL_SC_SetUartDiv()
855 clk=clk/1000; in HAL_SC_SetUartDiv()
856 u16div = (clk*u16ClkDiv)/(16*3375); in HAL_SC_SetUartDiv()
860 clk=clk/1000; in HAL_SC_SetUartDiv()
861 u16div = (clk*u16ClkDiv)/(16*4500); in HAL_SC_SetUartDiv()
865 clk=clk/1000; in HAL_SC_SetUartDiv()
866 u16div = (clk*u16ClkDiv)/(16*6750); in HAL_SC_SetUartDiv()
870 clk=clk/1000; in HAL_SC_SetUartDiv()
[all …]
/utopia/UTPA2-700.0.x/modules/mfe/drv/mfe_ex/
H A Dmdrv_mfe.c266 MS_U32 clk; in MDrv_MFE_GetBits() local
272 clk = 144; break; in MDrv_MFE_GetBits()
274 clk = 192; break; in MDrv_MFE_GetBits()
276 clk = 216; break; in MDrv_MFE_GetBits()
278 clk = 240; break; in MDrv_MFE_GetBits()
280 clk = 240; in MDrv_MFE_GetBits()
286 clk = 24; break; in MDrv_MFE_GetBits()
288 clk = 64; break; in MDrv_MFE_GetBits()
290 clk = 128; break; in MDrv_MFE_GetBits()
292 clk = 192; break; in MDrv_MFE_GetBits()
[all …]
/utopia/UTPA2-700.0.x/modules/dscmb/drv/nds/
H A Dnds_sc.c189 NDS_SC_Clk clk; member
234 .clk = E_NDS_SC_CLK_27M_D6,
1052 _nds_sc_dev.clk = E_NDS_SC_CLK_27M_D2; in HDICA_SetCardClockDivisor()
1055 _nds_sc_dev.clk = E_NDS_SC_CLK_27M_D4; in HDICA_SetCardClockDivisor()
1058 _nds_sc_dev.clk = E_NDS_SC_CLK_27M_D6; in HDICA_SetCardClockDivisor()
1065 if (!HAL_NDS_SC_SetClockDivisor(_nds_sc_dev.clk)) in HDICA_SetCardClockDivisor()
1111 switch (_nds_sc_dev.clk) in HDICA_SetUartBaudRate()
/utopia/UTPA2-700.0.x/modules/mspi/hal/M7621/mspi/
H A DhalMSPI.c645 MS_U32 clk =0; in HAL_MSPI_CLK_Config()
657 clk = clk_spi_m_p1[i]*1000000; in HAL_MSPI_CLK_Config()
661 … clk_buffer[k+MSPI_CLK_P1_MAX*j+MSPI_CLK_P2_MAX*i].u32ClkSpi = clk/((j+1)*(clk_spi_div[k])); in HAL_MSPI_CLK_Config()
/utopia/UTPA2-700.0.x/modules/mspi/hal/M7821/mspi/
H A DhalMSPI.c645 MS_U32 clk =0; in HAL_MSPI_CLK_Config()
657 clk = clk_spi_m_p1[i]*1000000; in HAL_MSPI_CLK_Config()
661 … clk_buffer[k+MSPI_CLK_P1_MAX*j+MSPI_CLK_P2_MAX*i].u32ClkSpi = clk/((j+1)*(clk_spi_div[k])); in HAL_MSPI_CLK_Config()
/utopia/UTPA2-700.0.x/modules/mspi/hal/manhattan/mspi/
H A DhalMSPI.c644 MS_U32 clk =0; in HAL_MSPI_CLK_Config() local
656 clk = clk_spi_m_p1[i]*1000000; in HAL_MSPI_CLK_Config()
660 … clk_buffer[k+MSPI_CLK_P1_MAX*j+MSPI_CLK_P2_MAX*i].u32ClkSpi = clk/((j+1)*(clk_spi_div[k])); in HAL_MSPI_CLK_Config()
/utopia/UTPA2-700.0.x/modules/mspi/hal/maxim/mspi/
H A DhalMSPI.c644 MS_U32 clk =0; in HAL_MSPI_CLK_Config() local
656 clk = clk_spi_m_p1[i]*1000000; in HAL_MSPI_CLK_Config()
660 … clk_buffer[k+MSPI_CLK_P1_MAX*j+MSPI_CLK_P2_MAX*i].u32ClkSpi = clk/((j+1)*(clk_spi_div[k])); in HAL_MSPI_CLK_Config()
/utopia/UTPA2-700.0.x/modules/mspi/hal/maserati/mspi/
H A DhalMSPI.c644 MS_U32 clk =0; in HAL_MSPI_CLK_Config() local
656 clk = clk_spi_m_p1[i]*1000000; in HAL_MSPI_CLK_Config()
660 … clk_buffer[k+MSPI_CLK_P1_MAX*j+MSPI_CLK_P2_MAX*i].u32ClkSpi = clk/((j+1)*(clk_spi_div[k])); in HAL_MSPI_CLK_Config()
/utopia/UTPA2-700.0.x/modules/sc/drv/sc/sc2/
H A DdrvSC.c734 MS_U32 clk = 144000000; in _SC_SetUartDiv() local
747 u16div = ((clk/3375000)*_scInfo[u8SCID].u16ClkDiv)/16; in _SC_SetUartDiv()
751 …u16div = ((clk/4500000)*_scInfo[u8SCID].u16ClkDiv)/16;//(108Mhz * 372) / (4.5Mhz * 16) <<--TOP_UAR… in _SC_SetUartDiv()
755 u16div = ((clk/6750000)*_scInfo[u8SCID].u16ClkDiv)/16; in _SC_SetUartDiv()
759 u16div = ((clk/16)*_scInfo[u8SCID].u16ClkDiv)/(3375000); in _SC_SetUartDiv()
763 …u16div = ((clk/4000000)*_scInfo[u8SCID].u16ClkDiv)/16;//(108Mhz * 372) / (4.5Mhz * 16) <<--TOP_UAR… in _SC_SetUartDiv()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h.0780 #define REG_CKG_IDCLK3 (REG_CHIPTOP_BASE + (0x56<<1) ) // sc dip top clk
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmdrv_sc_scaling.c.0196 #define MAX_1P_MODE_CLK 320000000 //(300*1024*1024) // max 1p mode clk value
3285 … // Consider Crop case, the post HSD clk is not enough for FRC enable case
10848 …)(u16Width)*(MS_U32)(u16Height)*(u32Vfreqx10/10)) >= MAX_1P_MODE_CLK))//ip clk >= 300Mhz, SC1 will…
10896 …else if(u32InputCLK >= MAX_1P_MODE_CLK)//ip clk >= 300Mhz,will be setted 2p mode.op clk>= ip clk,w…
H A Dmdrv_sc_display.c.04650 // Conver Phase to line base, phase(Xtal clk)
6426 // 4. control FRC clk
6649 …/*when scaler free run,stgen cant lock source for clk is not enough under 4k1k@120hz,4k0.5k@240 3d…
7025 …/*when scaler free run,stgen cant lock source for clk is not enough under 4k1k@120hz,4k0.5k@240 3d…
H A Dmvideo.c.01248 // copy from halpnl.c init xc clk condition, to set the subwindow Odclk.
6084 // 4. control FRC clk