Searched refs:_RegCtrl8 (Results 1 – 4 of 4) sorted by relevance
| /utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/ |
| H A D | halTSP.c | 47 static REG_Ctrl8* _RegCtrl8 = NULL; variable
188 _RegCtrl8 = (REG_Ctrl8*)(u32BankAddr + 0xE1A00UL); //TSP10 0x170D in HAL_TSP_SetBank()
5516 printf("SPS CTR mode = %p\n",&(_RegCtrl8[u32Eng].CFG8_05)); in HAL_TSP_PVR_SPSConfig()
5517 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_CTR_MODE_SPS_PVR1); //set CTR mode in HAL_TSP_PVR_SPSConfig()
5518 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[0]), 0x0000); //set counter IV in HAL_TSP_PVR_SPSConfig()
5519 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[1]), 0x0000); in HAL_TSP_PVR_SPSConfig()
5520 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[2]), 0x0000); in HAL_TSP_PVR_SPSConfig()
5521 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[3]), 0x0000); in HAL_TSP_PVR_SPSConfig()
5522 … REG16_W(&(_RegCtrl8[u32Eng].CFG8_04), CFG8_04_CTR_IV_SPS_MAX_1K); //set counter IV max vld in HAL_TSP_PVR_SPSConfig()
5523 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_LOAD_INIT_CNT_SPS1); //load counter IV in HAL_TSP_PVR_SPSConfig()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/ |
| H A D | halTSP.c | 60 static REG_Ctrl8* _RegCtrl8 = NULL; variable
216 _RegCtrl8 = (REG_Ctrl8*)(u32BankAddr + 0xE1A00UL); //TSP10 0x170D in HAL_TSP_SetBank()
6989 printf("SPS CTR mode = %p\n",&(_RegCtrl8[u32Eng].CFG8_05)); in HAL_TSP_PVR_SPSConfig()
6990 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_CTR_MODE_SPS_PVR1); //set CTR mode in HAL_TSP_PVR_SPSConfig()
6991 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[0]), 0x0000); //set counter IV in HAL_TSP_PVR_SPSConfig()
6992 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[1]), 0x0000); in HAL_TSP_PVR_SPSConfig()
6993 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[2]), 0x0000); in HAL_TSP_PVR_SPSConfig()
6994 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[3]), 0x0000); in HAL_TSP_PVR_SPSConfig()
6995 … REG16_W(&(_RegCtrl8[u32Eng].CFG8_04), CFG8_04_CTR_IV_SPS_MAX_1K); //set counter IV max vld in HAL_TSP_PVR_SPSConfig()
6996 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_LOAD_INIT_CNT_SPS1); //load counter IV in HAL_TSP_PVR_SPSConfig()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/ |
| H A D | halTSP.c | 52 static REG_Ctrl8* _RegCtrl8 = NULL; // TSP10 variable
195 _RegCtrl8 = (REG_Ctrl8*)(u32BankAddr + 0xE1A00UL); // TSP10 0x170D in HAL_TSP_SetBank()
7187 printf("SPS CTR mode = %p\n",&(_RegCtrl8[u32Eng].CFG8_05)); in HAL_TSP_PVR_SPSConfig()
7188 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_CTR_MODE_SPS_PVR1); //set CTR mode in HAL_TSP_PVR_SPSConfig()
7189 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[0]), 0x0000); //set counter IV in HAL_TSP_PVR_SPSConfig()
7190 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[1]), 0x0000); in HAL_TSP_PVR_SPSConfig()
7191 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[2]), 0x0000); in HAL_TSP_PVR_SPSConfig()
7192 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[3]), 0x0000); in HAL_TSP_PVR_SPSConfig()
7193 … REG16_W(&(_RegCtrl8[u32Eng].CFG8_04), CFG8_04_CTR_IV_SPS_MAX_1K); //set counter IV max vld in HAL_TSP_PVR_SPSConfig()
7194 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_LOAD_INIT_CNT_SPS1); //load counter IV in HAL_TSP_PVR_SPSConfig()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/ |
| H A D | halTSP.c | 56 static REG_Ctrl8* _RegCtrl8 = NULL; // TSP10 variable
213 _RegCtrl8 = (REG_Ctrl8*)(u32BankAddr + 0xE1A00UL); // TSP10 0x170D in HAL_TSP_SetBank()
7536 printf("SPS CTR mode = %p\n",&(_RegCtrl8[u32Eng].CFG8_05)); in HAL_TSP_PVR_SPSConfig()
7537 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_CTR_MODE_SPS_PVR1); //set CTR mode in HAL_TSP_PVR_SPSConfig()
7538 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[0]), 0x0000); //set counter IV in HAL_TSP_PVR_SPSConfig()
7539 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[1]), 0x0000); in HAL_TSP_PVR_SPSConfig()
7540 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[2]), 0x0000); in HAL_TSP_PVR_SPSConfig()
7541 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[3]), 0x0000); in HAL_TSP_PVR_SPSConfig()
7542 … REG16_W(&(_RegCtrl8[u32Eng].CFG8_04), CFG8_04_CTR_IV_SPS_MAX_1K); //set counter IV max vld in HAL_TSP_PVR_SPSConfig()
7543 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_LOAD_INIT_CNT_SPS1); //load counter IV in HAL_TSP_PVR_SPSConfig()
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