Searched refs:_RegCtrl7 (Results 1 – 4 of 4) sorted by relevance
| /utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/ |
| H A D | halTSP.c | 46 static REG_Ctrl7* _RegCtrl7 = NULL; variable
187 _RegCtrl7 = (REG_Ctrl7*)(u32BankAddr + 0xE1800UL); //TSP9 0x170C in HAL_TSP_SetBank()
4741 printf("SPD CTR mode = %p\n",&(_RegCtrl7[tsif].CFG7_05)); in HAL_TSP_FileIn_SPDConfig()
4742 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_CTR_MODE_SPD_FILEIN); //set CTR mode enable in HAL_TSP_FileIn_SPDConfig()
4743 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[0]), 0x0000); //set counter IV in HAL_TSP_FileIn_SPDConfig()
4744 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[1]), 0x0000); in HAL_TSP_FileIn_SPDConfig()
4745 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[2]), 0x0000); in HAL_TSP_FileIn_SPDConfig()
4746 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[3]), 0x0000); in HAL_TSP_FileIn_SPDConfig()
4747 REG16_W(&(_RegCtrl7[tsif].CFG7_04), CFG7_04_CTR_IV_SPD_MAX_1K); //set counter IV max vld in HAL_TSP_FileIn_SPDConfig()
4748 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_LOAD_INIT_CNT_SPD); //load counter IV in HAL_TSP_FileIn_SPDConfig()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/ |
| H A D | halTSP.c | 59 static REG_Ctrl7* _RegCtrl7 = NULL; variable
215 _RegCtrl7 = (REG_Ctrl7*)(u32BankAddr + 0xE1800UL); //TSP9 0x170C in HAL_TSP_SetBank()
6155 printf("SPD CTR mode = %p\n",&(_RegCtrl7[tsif].CFG7_05)); in HAL_TSP_FileIn_SPDConfig()
6156 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_CTR_MODE_SPD_FILEIN); //set CTR mode enable in HAL_TSP_FileIn_SPDConfig()
6157 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[0]), 0x0000); //set counter IV in HAL_TSP_FileIn_SPDConfig()
6158 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[1]), 0x0000); in HAL_TSP_FileIn_SPDConfig()
6159 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[2]), 0x0000); in HAL_TSP_FileIn_SPDConfig()
6160 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[3]), 0x0000); in HAL_TSP_FileIn_SPDConfig()
6161 REG16_W(&(_RegCtrl7[tsif].CFG7_04), CFG7_04_CTR_IV_SPD_MAX_1K); //set counter IV max vld in HAL_TSP_FileIn_SPDConfig()
6162 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_LOAD_INIT_CNT_SPD); //load counter IV in HAL_TSP_FileIn_SPDConfig()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/ |
| H A D | halTSP.c | 51 static REG_Ctrl7* _RegCtrl7 = NULL; // TSP9 variable
194 _RegCtrl7 = (REG_Ctrl7*)(u32BankAddr + 0xE1800UL); // TSP9 0x170C in HAL_TSP_SetBank()
6329 printf("SPD CTR mode = %p\n",&(_RegCtrl7[tsif].CFG7_05)); in HAL_TSP_FileIn_SPDConfig()
6330 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_CTR_MODE_SPD_FILEIN); //set CTR mode enable in HAL_TSP_FileIn_SPDConfig()
6331 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[0]), 0x0000); //set counter IV in HAL_TSP_FileIn_SPDConfig()
6332 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[1]), 0x0000); in HAL_TSP_FileIn_SPDConfig()
6333 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[2]), 0x0000); in HAL_TSP_FileIn_SPDConfig()
6334 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[3]), 0x0000); in HAL_TSP_FileIn_SPDConfig()
6335 REG16_W(&(_RegCtrl7[tsif].CFG7_04), CFG7_04_CTR_IV_SPD_MAX_1K); //set counter IV max vld in HAL_TSP_FileIn_SPDConfig()
6336 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_LOAD_INIT_CNT_SPD); //load counter IV in HAL_TSP_FileIn_SPDConfig()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/ |
| H A D | halTSP.c | 55 static REG_Ctrl7* _RegCtrl7 = NULL; // TSP9 variable
212 _RegCtrl7 = (REG_Ctrl7*)(u32BankAddr + 0xE1800UL); // TSP9 0x170C in HAL_TSP_SetBank()
6701 printf("SPD CTR mode = %p\n",&(_RegCtrl7[tsif].CFG7_05)); in HAL_TSP_FileIn_SPDConfig()
6702 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_CTR_MODE_SPD_FILEIN); //set CTR mode enable in HAL_TSP_FileIn_SPDConfig()
6703 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[0]), 0x0000); //set counter IV in HAL_TSP_FileIn_SPDConfig()
6704 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[1]), 0x0000); in HAL_TSP_FileIn_SPDConfig()
6705 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[2]), 0x0000); in HAL_TSP_FileIn_SPDConfig()
6706 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[3]), 0x0000); in HAL_TSP_FileIn_SPDConfig()
6707 REG16_W(&(_RegCtrl7[tsif].CFG7_04), CFG7_04_CTR_IV_SPD_MAX_1K); //set counter IV max vld in HAL_TSP_FileIn_SPDConfig()
6708 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_LOAD_INIT_CNT_SPD); //load counter IV in HAL_TSP_FileIn_SPDConfig()
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