Searched refs:REG_WR (Results 1 – 2 of 2) sorted by relevance
| /utopia/UTPA2-700.0.x/modules/graphic/drv/ge/ |
| H A D | drvGE.c | 5192 #define REG_WR(_reg_, _val_) do{ REG_ADDR(_reg_) = (_val_); }while(0) macro
5278 REG_WR(0x1012FE, 0x011E); //priority 2>3>1>0 in MDrv_GE_BitbltPerformance()
5279 REG_WR(0x101240, 0x8011); //disable flow control group 0/1/2 in MDrv_GE_BitbltPerformance()
5280 REG_WR(0x101260, 0x8011); in MDrv_GE_BitbltPerformance()
5281 REG_WR(0x101280, 0x8011); in MDrv_GE_BitbltPerformance()
5283 REG_WR(0x1012FC, 0xA400); //FIFO32 in MDrv_GE_BitbltPerformance()
5284 REG_WR(0x101228, 0x4090); //PACK enable in MDrv_GE_BitbltPerformance()
5287 REG_WR(0x1012FE, 0x00D2); //priority 2>0>1>3 in MDrv_GE_BitbltPerformance()
5288 REG_WR(0x101240, 0x8011); //disable flow control in MDrv_GE_BitbltPerformance()
5289 REG_WR(0x101260, 0x8011); in MDrv_GE_BitbltPerformance()
[all …]
|
| /utopia/UTPA2-700.0.x/modules/mfe/drv/mfe/ |
| H A D | mdrv_mfe.c | 241 REG_WR(REG_PIU_TIMER0(0x00), 0x0); in MFE_MsOS_START_TIMER()
242 REG_WR(REG_PIU_TIMER0(0x00), 0x1); in MFE_MsOS_START_TIMER()
|