Lines Matching refs:REG_WR
5192 #define REG_WR(_reg_, _val_) do{ REG_ADDR(_reg_) = (_val_); }while(0) macro
5278 REG_WR(0x1012FE, 0x011E); //priority 2>3>1>0 in MDrv_GE_BitbltPerformance()
5279 REG_WR(0x101240, 0x8011); //disable flow control group 0/1/2 in MDrv_GE_BitbltPerformance()
5280 REG_WR(0x101260, 0x8011); in MDrv_GE_BitbltPerformance()
5281 REG_WR(0x101280, 0x8011); in MDrv_GE_BitbltPerformance()
5283 REG_WR(0x1012FC, 0xA400); //FIFO32 in MDrv_GE_BitbltPerformance()
5284 REG_WR(0x101228, 0x4090); //PACK enable in MDrv_GE_BitbltPerformance()
5287 REG_WR(0x1012FE, 0x00D2); //priority 2>0>1>3 in MDrv_GE_BitbltPerformance()
5288 REG_WR(0x101240, 0x8011); //disable flow control in MDrv_GE_BitbltPerformance()
5289 REG_WR(0x101260, 0x8011); in MDrv_GE_BitbltPerformance()
5290 REG_WR(0x101280, 0x8011); in MDrv_GE_BitbltPerformance()
5292 REG_WR(0x1012FC, 0xA400); //FIFO32 in MDrv_GE_BitbltPerformance()
5293 REG_WR(0x101228, 0x4000); //PACK enable in MDrv_GE_BitbltPerformance()
5295 REG_WR(0x101246, 0xffff); in MDrv_GE_BitbltPerformance()
5296 REG_WR(0x101248, 0x0000); in MDrv_GE_BitbltPerformance()
5297 REG_WR(0x101266, 0xffff); in MDrv_GE_BitbltPerformance()
5298 REG_WR(0x101268, 0x0000); in MDrv_GE_BitbltPerformance()
5424 REG_WR(REG_MIU0_GROUP0_MASK, 0xFFF8); //enable miu counter in MDrv_GE_BitbltPerformance()
5425 REG_WR(REG_MIU0_GROUP1_MASK, 0xFFFF); //enable miu counter in MDrv_GE_BitbltPerformance()
5426 REG_WR(REG_MIU0_GROUP2_MASK, 0xFFFE); //enable miu counter in MDrv_GE_BitbltPerformance()
5427 REG_WR(REG_MIU0_GROUP3_MASK, 0xFFFE); //enable miu counter in MDrv_GE_BitbltPerformance()
5429 REG_WR(REG_MIU1_GROUP0_MASK, 0xFFF8); //enable miu counter in MDrv_GE_BitbltPerformance()
5430 REG_WR(REG_MIU1_GROUP1_MASK, 0xFFFF); //enable miu counter in MDrv_GE_BitbltPerformance()
5431 REG_WR(REG_MIU1_GROUP2_MASK, 0xFFFE); //enable miu counter in MDrv_GE_BitbltPerformance()
5432 REG_WR(REG_MIU1_GROUP3_MASK, 0xFFFE); //enable miu counter in MDrv_GE_BitbltPerformance()
5544 REG_WR(REG_MIU0_CTRL, 0x50 | GE_group_client); //enable miu counter in MDrv_GE_BitbltPerformance()
5545 REG_WR(REG_MIU0_CTRL, 0x51 | GE_group_client); //enable miu counter in MDrv_GE_BitbltPerformance()
5549 REG_WR(REG_MIU1_CTRL, 0x50 | GE_group_client); //enable miu counter in MDrv_GE_BitbltPerformance()
5550 REG_WR(REG_MIU1_CTRL, 0x51 | GE_group_client); //enable miu counter in MDrv_GE_BitbltPerformance()
5554 REG_WR(REG_PIU_TIMER0(0x02), 0xFFFF); in MDrv_GE_BitbltPerformance()
5555 REG_WR(REG_PIU_TIMER0(0x03), 0xFFFF); in MDrv_GE_BitbltPerformance()
5557 REG_WR(REG_PIU_TIMER0(0x00), 0x0); in MDrv_GE_BitbltPerformance()
5558 REG_WR(REG_PIU_TIMER0(0x00), 0x1); in MDrv_GE_BitbltPerformance()
5671 REG_WR(REG_PIU_TIMER0(0x00), 0x0); in MDrv_GE_BitbltPerformance()
5672 REG_WR(REG_PIU_TIMER0(0x00), 0x1); in MDrv_GE_BitbltPerformance()