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Searched refs:REG_SC_BKC6_D0 (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_4K2K.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
808 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_2D_4K2K_2D_FHD_YUV()
809 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_4K2K_2D_FHD_YUV()
810 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_4K2K_2D_FHD_YUV()
1229 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1230 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1231 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1650 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_2D_4K2K_2D_4K2K_YUV()
[all …]
H A DMaserati_2D_FHD.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
808 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_2D_FHD_2D_FHD_YUV()
809 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_FHD_2D_FHD_YUV()
810 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_ACT_4K0_5K.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K1K_LLRR_240.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaserati_ACT_4K1K.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K2K_120.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_120.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K0_5K_LLRR_240.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K1K_120.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_60.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A Dhwreg_frc_map.h13374 #define REG_SC_BKC6_D0 (REG_SCALER_BASE+0xC6D0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_4K2K.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
808 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_2D_4K2K_2D_FHD_YUV()
809 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_4K2K_2D_FHD_YUV()
810 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_4K2K_2D_FHD_YUV()
1229 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1230 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1231 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1650 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_2D_4K2K_2D_4K2K_YUV()
[all …]
H A DMaserati_2D_FHD.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
808 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_2D_FHD_2D_FHD_YUV()
809 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_2D_FHD_2D_FHD_YUV()
810 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_ACT_4K1K.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K2K_120.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K0_5K_LLRR_240.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_60.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K1K_120.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_120.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaserati_ACT_4K0_5K.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K1K_LLRR_240.c387 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x01); // reg_render_control in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
388 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x00, 0x02); // reg_lr_control_l in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
389 MDrv_WriteByteMask( REG_SC_BKC6_D0, 0x04, 0x04); // reg_lr_control_r in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A Dhwreg_frc_map.h13374 #define REG_SC_BKC6_D0 (REG_SCALER_BASE+0xC6D0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_frc_map.h11305 #define REG_SC_BKC6_D0 (REG_SCALER_BASE+0xC6D0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_frc_map.h11305 #define REG_SC_BKC6_D0 (REG_SCALER_BASE+0xC6D0) macro