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Searched refs:REG_SC_BKC6_C2 (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_4K2K.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
801 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_2D_4K2K_2D_FHD_YUV()
1222 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1643 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_2D_4K2K_2D_4K2K_YUV()
2064 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2485 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x80, 0xff); // reg_ln_width in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
801 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x80, 0xff); // reg_ln_width in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_ACT_4K0_5K.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K1K_LLRR_240.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaserati_ACT_4K1K.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K2K_120.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_120.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K0_5K_LLRR_240.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K1K_120.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_60.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A Dhwreg_frc_map.h13360 #define REG_SC_BKC6_C2 (REG_SCALER_BASE+0xC6C2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_4K2K.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
801 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_2D_4K2K_2D_FHD_YUV()
1222 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1643 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_2D_4K2K_2D_4K2K_YUV()
2064 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2485 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x80, 0xff); // reg_ln_width in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
801 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x80, 0xff); // reg_ln_width in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_ACT_4K1K.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K2K_120.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K0_5K_LLRR_240.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_60.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K1K_120.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_120.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaserati_ACT_4K0_5K.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K1K_LLRR_240.c380 MDrv_WriteByteMask( REG_SC_BKC6_C2, 0x00, 0xff); // reg_ln_width in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A Dhwreg_frc_map.h13360 #define REG_SC_BKC6_C2 (REG_SCALER_BASE+0xC6C2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_frc_map.h11291 #define REG_SC_BKC6_C2 (REG_SCALER_BASE+0xC6C2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_frc_map.h11291 #define REG_SC_BKC6_C2 (REG_SCALER_BASE+0xC6C2) macro