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Searched refs:REG_SC_BK03_48_L (Results 1 – 25 of 67) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_ip.c1948 SC_W2BYTEMSK(0,REG_SC_BK03_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
1964 SC_W2BYTEMSK(0,REG_SC_BK03_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
1980 SC_W2BYTEMSK(0,REG_SC_BK03_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
1996 SC_W2BYTEMSK(0,REG_SC_BK03_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2012 SC_W2BYTEMSK(0,REG_SC_BK03_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2028 SC_W2BYTEMSK(0,REG_SC_BK03_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_ip.c1948 SC_W2BYTEMSK(0,REG_SC_BK03_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
1964 SC_W2BYTEMSK(0,REG_SC_BK03_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
1980 SC_W2BYTEMSK(0,REG_SC_BK03_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
1996 SC_W2BYTEMSK(0,REG_SC_BK03_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2012 SC_W2BYTEMSK(0,REG_SC_BK03_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2028 SC_W2BYTEMSK(0,REG_SC_BK03_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_ip.c2354 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2372 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2390 … SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2408 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2426 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2444 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_ip.c2434 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2450 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2466 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2482 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2498 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2514 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_ip.c2414 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2430 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2446 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2462 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2478 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2494 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_ip.c2421 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2437 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2453 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2469 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2485 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2501 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_ip.c2412 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2428 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2444 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2460 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2476 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2492 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_ip.c2423 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2439 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2455 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2471 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2487 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2503 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_ip.c2327 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2345 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2363 … SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2381 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2399 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2417 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_ip.c2327 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2345 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2363 … SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2381 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2399 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2417 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_ip.c2380 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2396 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2412 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2428 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2444 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2460 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_ip.c2327 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2345 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2363 … SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2381 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2399 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2417 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_ip.c2409 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2425 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2441 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2457 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2473 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2489 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_ip.c2380 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2396 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2412 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2428 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2444 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2460 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_ip.c2434 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2450 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2466 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2482 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2498 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2514 SC_W2BYTEMSK(0, REG_SC_BK03_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/wble/hal/manhattan/wble/include/
H A Dhwreg_wble.h1036 #define REG_SC_BK03_48_L _PK_L_(0x03, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/ace/include/
H A Dhwreg_ace.h1036 #define REG_SC_BK03_48_L _PK_L_(0x03, 0x48) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/
H A Dhwreg_dlc.h1038 #define REG_SC_BK03_48_L _PK_L_(0x03, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/include/
H A Dhwreg_ace.h1036 #define REG_SC_BK03_48_L _PK_L_(0x03, 0x48) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/
H A Dhwreg_dlc.h1038 #define REG_SC_BK03_48_L _PK_L_(0x03, 0x48) macro
/utopia/UTPA2-700.0.x/modules/wble/hal/macan/wble/include/
H A Dhwreg_wble.h1036 #define REG_SC_BK03_48_L _PK_L_(0x03, 0x48) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/curry/dlc/include/
H A Dhwreg_dlc.h1038 #define REG_SC_BK03_48_L _PK_L_(0x03, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/ace/include/
H A Dhwreg_ace.h1036 #define REG_SC_BK03_48_L _PK_L_(0x03, 0x48) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/M7821/dlc/include/
H A Dhwreg_dlc.h1038 #define REG_SC_BK03_48_L _PK_L_(0x03, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/ace/include/
H A Dhwreg_ace.h1036 #define REG_SC_BK03_48_L _PK_L_(0x03, 0x48) macro

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