Home
last modified time | relevance | path

Searched refs:REG_SC_BK03_26_L (Results 1 – 25 of 67) sorted by relevance

123

/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_ip.c1009 SC_W2BYTEMSK(0, REG_SC_BK03_26_L, (bMode<<2), BIT(2) ); in Hal_SC_ip_set_input_sync_sample_mode()
1102 SC_W2BYTEMSK(0, REG_SC_BK03_26_L, ((bEnble<<7)|((u8Range&0x07)<<4)), 0xF0 ); in Hal_SC_ip_set_post_glitch_removal()
1124 bEnable = (MS_BOOL)(SC_R2BYTEMSK(0,REG_SC_BK03_26_L, BIT(7)) >> 7); in Hal_SC_ip_get_post_glitch_removal()
1127 return (MS_U8)(SC_R2BYTEMSK(0,REG_SC_BK03_26_L, BIT(6)|BIT(5)|BIT(4)) >> 4); in Hal_SC_ip_get_post_glitch_removal()
1793 SC_W2BYTE(0,REG_SC_BK03_26_L, value); in HAL_SC_ip_3DMainSub_IPSync()
2039 SC_W2BYTEMSK(0, REG_SC_BK03_26_L, (bEnable?BIT(8):0), BIT(8)); in HAL_SC_ip_Set_FD_Mask_ByWin()
2057 if(SC_R2BYTEMSK(0, REG_SC_BK03_26_L, BIT(8))) in HAL_SC_ip_Get_FD_Mask_ByWin()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_ip.c1009 SC_W2BYTEMSK(0, REG_SC_BK03_26_L, (bMode<<2), BIT(2) ); in Hal_SC_ip_set_input_sync_sample_mode()
1102 SC_W2BYTEMSK(0, REG_SC_BK03_26_L, ((bEnble<<7)|((u8Range&0x07)<<4)), 0xF0 ); in Hal_SC_ip_set_post_glitch_removal()
1124 bEnable = (MS_BOOL)(SC_R2BYTEMSK(0,REG_SC_BK03_26_L, BIT(7)) >> 7); in Hal_SC_ip_get_post_glitch_removal()
1127 return (MS_U8)(SC_R2BYTEMSK(0,REG_SC_BK03_26_L, BIT(6)|BIT(5)|BIT(4)) >> 4); in Hal_SC_ip_get_post_glitch_removal()
1793 SC_W2BYTE(0,REG_SC_BK03_26_L, value); in HAL_SC_ip_3DMainSub_IPSync()
2039 SC_W2BYTEMSK(0, REG_SC_BK03_26_L, (bEnable?BIT(8):0), BIT(8)); in HAL_SC_ip_Set_FD_Mask_ByWin()
2057 if(SC_R2BYTEMSK(0, REG_SC_BK03_26_L, BIT(8))) in HAL_SC_ip_Get_FD_Mask_ByWin()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_ip.c987 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bMode<<2), BIT(2) ); in Hal_SC_ip_set_input_sync_sample_mode()
1091 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, ((bEnble<<7)|((u8Range&0x07)<<4)), 0xF0 … in Hal_SC_ip_set_post_glitch_removal()
1115 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(7)) >> 7); in Hal_SC_ip_get_post_glitch_removal()
1118 …return (MS_U8)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(6)|BIT(5)|BIT(4)) >> 4… in Hal_SC_ip_get_post_glitch_removal()
2093 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, value); in HAL_SC_ip_3DMainSub_IPSync()
2277 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bEnable?BIT(8):0), BIT(8)); in HAL_SC_ip_Set_FD_Mask_ByWin()
2298 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(8))) in HAL_SC_ip_Get_FD_Mask_ByWin()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_ip.c1120 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bMode<<2), BIT(2) ); in Hal_SC_ip_set_input_sync_sample_mode()
1224 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, ((bEnble<<7)|((u8Range&0x07)<<4)), 0xF0 … in Hal_SC_ip_set_post_glitch_removal()
1248 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(7)) >> 7); in Hal_SC_ip_get_post_glitch_removal()
1251 …return (MS_U8)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(6)|BIT(5)|BIT(4)) >> 4… in Hal_SC_ip_get_post_glitch_removal()
2224 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, value); in HAL_SC_ip_3DMainSub_IPSync()
2371 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bEnable?BIT(8):0), BIT(8)); in HAL_SC_ip_Set_FD_Mask_ByWin()
2397 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(8))) in HAL_SC_ip_Get_FD_Mask_ByWin()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_ip.c1167 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bMode<<2), BIT(2) ); in Hal_SC_ip_set_input_sync_sample_mode()
1243 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, ((bEnble<<7)|((u8Range&0x07)<<4)), 0xF0 … in Hal_SC_ip_set_post_glitch_removal()
1267 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(7)) >> 7); in Hal_SC_ip_get_post_glitch_removal()
1270 …return (MS_U8)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(6)|BIT(5)|BIT(4)) >> 4… in Hal_SC_ip_get_post_glitch_removal()
2218 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, value); in HAL_SC_ip_3DMainSub_IPSync()
2360 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bEnable?BIT(8):0), BIT(8)); in HAL_SC_ip_Set_FD_Mask_ByWin()
2386 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(8))) in HAL_SC_ip_Get_FD_Mask_ByWin()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_ip.c1120 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bMode<<2), BIT(2) ); in Hal_SC_ip_set_input_sync_sample_mode()
1224 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, ((bEnble<<7)|((u8Range&0x07)<<4)), 0xF0 … in Hal_SC_ip_set_post_glitch_removal()
1248 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(7)) >> 7); in Hal_SC_ip_get_post_glitch_removal()
1251 …return (MS_U8)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(6)|BIT(5)|BIT(4)) >> 4… in Hal_SC_ip_get_post_glitch_removal()
2211 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, value); in HAL_SC_ip_3DMainSub_IPSync()
2358 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bEnable?BIT(8):0), BIT(8)); in HAL_SC_ip_Set_FD_Mask_ByWin()
2384 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(8))) in HAL_SC_ip_Get_FD_Mask_ByWin()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_ip.c1120 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bMode<<2), BIT(2) ); in Hal_SC_ip_set_input_sync_sample_mode()
1224 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, ((bEnble<<7)|((u8Range&0x07)<<4)), 0xF0 … in Hal_SC_ip_set_post_glitch_removal()
1248 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(7)) >> 7); in Hal_SC_ip_get_post_glitch_removal()
1251 …return (MS_U8)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(6)|BIT(5)|BIT(4)) >> 4… in Hal_SC_ip_get_post_glitch_removal()
2211 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, value); in HAL_SC_ip_3DMainSub_IPSync()
2358 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bEnable?BIT(8):0), BIT(8)); in HAL_SC_ip_Set_FD_Mask_ByWin()
2384 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(8))) in HAL_SC_ip_Get_FD_Mask_ByWin()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_ip.c1124 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bMode<<2), BIT(2) ); in Hal_SC_ip_set_input_sync_sample_mode()
1228 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, ((bEnble<<7)|((u8Range&0x07)<<4)), 0xF0 … in Hal_SC_ip_set_post_glitch_removal()
1252 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(7)) >> 7); in Hal_SC_ip_get_post_glitch_removal()
1255 …return (MS_U8)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(6)|BIT(5)|BIT(4)) >> 4… in Hal_SC_ip_get_post_glitch_removal()
2213 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, value); in HAL_SC_ip_3DMainSub_IPSync()
2360 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bEnable?BIT(8):0), BIT(8)); in HAL_SC_ip_Set_FD_Mask_ByWin()
2386 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(8))) in HAL_SC_ip_Get_FD_Mask_ByWin()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_ip.c987 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bMode<<2), BIT(2) ); in Hal_SC_ip_set_input_sync_sample_mode()
1091 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, ((bEnble<<7)|((u8Range&0x07)<<4)), 0xF0 … in Hal_SC_ip_set_post_glitch_removal()
1115 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(7)) >> 7); in Hal_SC_ip_get_post_glitch_removal()
1118 …return (MS_U8)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(6)|BIT(5)|BIT(4)) >> 4… in Hal_SC_ip_get_post_glitch_removal()
2092 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, value); in HAL_SC_ip_3DMainSub_IPSync()
2250 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bEnable?BIT(8):0), BIT(8)); in HAL_SC_ip_Set_FD_Mask_ByWin()
2271 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(8))) in HAL_SC_ip_Get_FD_Mask_ByWin()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_ip.c987 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bMode<<2), BIT(2) ); in Hal_SC_ip_set_input_sync_sample_mode()
1091 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, ((bEnble<<7)|((u8Range&0x07)<<4)), 0xF0 … in Hal_SC_ip_set_post_glitch_removal()
1115 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(7)) >> 7); in Hal_SC_ip_get_post_glitch_removal()
1118 …return (MS_U8)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(6)|BIT(5)|BIT(4)) >> 4… in Hal_SC_ip_get_post_glitch_removal()
2092 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, value); in HAL_SC_ip_3DMainSub_IPSync()
2250 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bEnable?BIT(8):0), BIT(8)); in HAL_SC_ip_Set_FD_Mask_ByWin()
2271 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(8))) in HAL_SC_ip_Get_FD_Mask_ByWin()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_ip.c1123 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bMode<<2), BIT(2) ); in Hal_SC_ip_set_input_sync_sample_mode()
1199 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, ((bEnble<<7)|((u8Range&0x07)<<4)), 0xF0 … in Hal_SC_ip_set_post_glitch_removal()
1223 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(7)) >> 7); in Hal_SC_ip_get_post_glitch_removal()
1226 …return (MS_U8)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(6)|BIT(5)|BIT(4)) >> 4… in Hal_SC_ip_get_post_glitch_removal()
2184 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, value); in HAL_SC_ip_3DMainSub_IPSync()
2326 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bEnable?BIT(8):0), BIT(8)); in HAL_SC_ip_Set_FD_Mask_ByWin()
2352 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(8))) in HAL_SC_ip_Get_FD_Mask_ByWin()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_ip.c987 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bMode<<2), BIT(2) ); in Hal_SC_ip_set_input_sync_sample_mode()
1091 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, ((bEnble<<7)|((u8Range&0x07)<<4)), 0xF0 … in Hal_SC_ip_set_post_glitch_removal()
1115 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(7)) >> 7); in Hal_SC_ip_get_post_glitch_removal()
1118 …return (MS_U8)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(6)|BIT(5)|BIT(4)) >> 4… in Hal_SC_ip_get_post_glitch_removal()
2092 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, value); in HAL_SC_ip_3DMainSub_IPSync()
2250 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bEnable?BIT(8):0), BIT(8)); in HAL_SC_ip_Set_FD_Mask_ByWin()
2271 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(8))) in HAL_SC_ip_Get_FD_Mask_ByWin()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_ip.c1124 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bMode<<2), BIT(2) ); in Hal_SC_ip_set_input_sync_sample_mode()
1228 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, ((bEnble<<7)|((u8Range&0x07)<<4)), 0xF0 … in Hal_SC_ip_set_post_glitch_removal()
1252 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(7)) >> 7); in Hal_SC_ip_get_post_glitch_removal()
1255 …return (MS_U8)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(6)|BIT(5)|BIT(4)) >> 4… in Hal_SC_ip_get_post_glitch_removal()
2213 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, value); in HAL_SC_ip_3DMainSub_IPSync()
2355 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bEnable?BIT(8):0), BIT(8)); in HAL_SC_ip_Set_FD_Mask_ByWin()
2381 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(8))) in HAL_SC_ip_Get_FD_Mask_ByWin()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_ip.c1123 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bMode<<2), BIT(2) ); in Hal_SC_ip_set_input_sync_sample_mode()
1199 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, ((bEnble<<7)|((u8Range&0x07)<<4)), 0xF0 … in Hal_SC_ip_set_post_glitch_removal()
1223 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(7)) >> 7); in Hal_SC_ip_get_post_glitch_removal()
1226 …return (MS_U8)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(6)|BIT(5)|BIT(4)) >> 4… in Hal_SC_ip_get_post_glitch_removal()
2184 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, value); in HAL_SC_ip_3DMainSub_IPSync()
2326 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bEnable?BIT(8):0), BIT(8)); in HAL_SC_ip_Set_FD_Mask_ByWin()
2352 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(8))) in HAL_SC_ip_Get_FD_Mask_ByWin()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_ip.c1120 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bMode<<2), BIT(2) ); in Hal_SC_ip_set_input_sync_sample_mode()
1224 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, ((bEnble<<7)|((u8Range&0x07)<<4)), 0xF0 … in Hal_SC_ip_set_post_glitch_removal()
1248 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(7)) >> 7); in Hal_SC_ip_get_post_glitch_removal()
1251 …return (MS_U8)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(6)|BIT(5)|BIT(4)) >> 4… in Hal_SC_ip_get_post_glitch_removal()
2224 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, value); in HAL_SC_ip_3DMainSub_IPSync()
2371 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, (bEnable?BIT(8):0), BIT(8)); in HAL_SC_ip_Set_FD_Mask_ByWin()
2397 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_26_L, BIT(8))) in HAL_SC_ip_Get_FD_Mask_ByWin()
/utopia/UTPA2-700.0.x/modules/wble/hal/manhattan/wble/include/
H A Dhwreg_wble.h968 #define REG_SC_BK03_26_L _PK_L_(0x03, 0x26) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/ace/include/
H A Dhwreg_ace.h968 #define REG_SC_BK03_26_L _PK_L_(0x03, 0x26) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/
H A Dhwreg_dlc.h970 #define REG_SC_BK03_26_L _PK_L_(0x03, 0x26) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/include/
H A Dhwreg_ace.h968 #define REG_SC_BK03_26_L _PK_L_(0x03, 0x26) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/
H A Dhwreg_dlc.h970 #define REG_SC_BK03_26_L _PK_L_(0x03, 0x26) macro
/utopia/UTPA2-700.0.x/modules/wble/hal/macan/wble/include/
H A Dhwreg_wble.h968 #define REG_SC_BK03_26_L _PK_L_(0x03, 0x26) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/curry/dlc/include/
H A Dhwreg_dlc.h970 #define REG_SC_BK03_26_L _PK_L_(0x03, 0x26) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/ace/include/
H A Dhwreg_ace.h968 #define REG_SC_BK03_26_L _PK_L_(0x03, 0x26) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/M7821/dlc/include/
H A Dhwreg_dlc.h970 #define REG_SC_BK03_26_L _PK_L_(0x03, 0x26) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/ace/include/
H A Dhwreg_ace.h968 #define REG_SC_BK03_26_L _PK_L_(0x03, 0x26) macro

123