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Searched refs:REG_PM_SLP_BASE (Results 1 – 25 of 43) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_offline.c313 W2BYTEMSK(REG_PM_SLP_BASE+0x94,0,BIT(12 + u8Tmp)); in Hal_XC_SetOffLineToHDMI()
317 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(0)|BIT(4)|BIT(8)|BIT(12))); in Hal_XC_SetOffLineToHDMI()
320 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(1)|BIT(5)|BIT(9)|BIT(13))); in Hal_XC_SetOffLineToHDMI()
323 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(2)|BIT(6)|BIT(10)|BIT(14))); in Hal_XC_SetOffLineToHDMI()
326 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(3)|BIT(7)|BIT(11)|BIT(15))); in Hal_XC_SetOffLineToHDMI()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_offline.c319 W2BYTEMSK(REG_PM_SLP_BASE+0x94,0,BIT(12 + u8Tmp)); in Hal_XC_SetOffLineToHDMI()
323 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(0)|BIT(4)|BIT(8)|BIT(12))); in Hal_XC_SetOffLineToHDMI()
326 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(1)|BIT(5)|BIT(9)|BIT(13))); in Hal_XC_SetOffLineToHDMI()
329 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(2)|BIT(6)|BIT(10)|BIT(14))); in Hal_XC_SetOffLineToHDMI()
332 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(3)|BIT(7)|BIT(11)|BIT(15))); in Hal_XC_SetOffLineToHDMI()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_offline.c313 W2BYTEMSK(REG_PM_SLP_BASE+0x94,0,BIT(12 + u8Tmp)); in Hal_XC_SetOffLineToHDMI()
317 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(0)|BIT(4)|BIT(8)|BIT(12))); in Hal_XC_SetOffLineToHDMI()
320 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(1)|BIT(5)|BIT(9)|BIT(13))); in Hal_XC_SetOffLineToHDMI()
323 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(2)|BIT(6)|BIT(10)|BIT(14))); in Hal_XC_SetOffLineToHDMI()
326 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(3)|BIT(7)|BIT(11)|BIT(15))); in Hal_XC_SetOffLineToHDMI()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_offline.c292 W2BYTEMSK(REG_PM_SLP_BASE+0x94,0,BIT(12 + u8Tmp)); in Hal_XC_SetOffLineToHDMI()
296 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(0)|BIT(4)|BIT(8)|BIT(12))); in Hal_XC_SetOffLineToHDMI()
299 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(1)|BIT(5)|BIT(9)|BIT(13))); in Hal_XC_SetOffLineToHDMI()
302 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(2)|BIT(6)|BIT(10)|BIT(14))); in Hal_XC_SetOffLineToHDMI()
305 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(3)|BIT(7)|BIT(11)|BIT(15))); in Hal_XC_SetOffLineToHDMI()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_offline.c292 W2BYTEMSK(REG_PM_SLP_BASE+0x94,0,BIT(12 + u8Tmp)); in Hal_XC_SetOffLineToHDMI()
296 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(0)|BIT(4)|BIT(8)|BIT(12))); in Hal_XC_SetOffLineToHDMI()
299 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(1)|BIT(5)|BIT(9)|BIT(13))); in Hal_XC_SetOffLineToHDMI()
302 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(2)|BIT(6)|BIT(10)|BIT(14))); in Hal_XC_SetOffLineToHDMI()
305 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(3)|BIT(7)|BIT(11)|BIT(15))); in Hal_XC_SetOffLineToHDMI()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_offline.c319 W2BYTEMSK(REG_PM_SLP_BASE+0x94,0,BIT(12 + u8Tmp)); in Hal_XC_SetOffLineToHDMI()
323 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(0)|BIT(4)|BIT(8)|BIT(12))); in Hal_XC_SetOffLineToHDMI()
326 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(1)|BIT(5)|BIT(9)|BIT(13))); in Hal_XC_SetOffLineToHDMI()
329 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(2)|BIT(6)|BIT(10)|BIT(14))); in Hal_XC_SetOffLineToHDMI()
332 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(3)|BIT(7)|BIT(11)|BIT(15))); in Hal_XC_SetOffLineToHDMI()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_offline.c319 W2BYTEMSK(REG_PM_SLP_BASE+0x94,0,BIT(12 + u8Tmp)); in Hal_XC_SetOffLineToHDMI()
323 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(0)|BIT(4)|BIT(8)|BIT(12))); in Hal_XC_SetOffLineToHDMI()
326 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(1)|BIT(5)|BIT(9)|BIT(13))); in Hal_XC_SetOffLineToHDMI()
329 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(2)|BIT(6)|BIT(10)|BIT(14))); in Hal_XC_SetOffLineToHDMI()
332 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(3)|BIT(7)|BIT(11)|BIT(15))); in Hal_XC_SetOffLineToHDMI()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_offline.c319 W2BYTEMSK(REG_PM_SLP_BASE+0x94,0,BIT(12 + u8Tmp)); in Hal_XC_SetOffLineToHDMI()
323 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(0)|BIT(4)|BIT(8)|BIT(12))); in Hal_XC_SetOffLineToHDMI()
326 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(1)|BIT(5)|BIT(9)|BIT(13))); in Hal_XC_SetOffLineToHDMI()
329 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(2)|BIT(6)|BIT(10)|BIT(14))); in Hal_XC_SetOffLineToHDMI()
332 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(3)|BIT(7)|BIT(11)|BIT(15))); in Hal_XC_SetOffLineToHDMI()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_offline.c319 W2BYTEMSK(REG_PM_SLP_BASE+0x94,0,BIT(12 + u8Tmp)); in Hal_XC_SetOffLineToHDMI()
323 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(0)|BIT(4)|BIT(8)|BIT(12))); in Hal_XC_SetOffLineToHDMI()
326 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(1)|BIT(5)|BIT(9)|BIT(13))); in Hal_XC_SetOffLineToHDMI()
329 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(2)|BIT(6)|BIT(10)|BIT(14))); in Hal_XC_SetOffLineToHDMI()
332 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(3)|BIT(7)|BIT(11)|BIT(15))); in Hal_XC_SetOffLineToHDMI()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_offline.c319 W2BYTEMSK(REG_PM_SLP_BASE+0x94,0,BIT(12 + u8Tmp)); in Hal_XC_SetOffLineToHDMI()
323 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(0)|BIT(4)|BIT(8)|BIT(12))); in Hal_XC_SetOffLineToHDMI()
326 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(1)|BIT(5)|BIT(9)|BIT(13))); in Hal_XC_SetOffLineToHDMI()
329 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(2)|BIT(6)|BIT(10)|BIT(14))); in Hal_XC_SetOffLineToHDMI()
332 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(3)|BIT(7)|BIT(11)|BIT(15))); in Hal_XC_SetOffLineToHDMI()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_offline.c316 W2BYTEMSK(REG_PM_SLP_BASE+0x94,0,BIT(12 + u8Tmp)); in Hal_XC_SetOffLineToHDMI()
320 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(0)|BIT(4)|BIT(8)|BIT(12))); in Hal_XC_SetOffLineToHDMI()
323 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(1)|BIT(5)|BIT(9)|BIT(13))); in Hal_XC_SetOffLineToHDMI()
326 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(2)|BIT(6)|BIT(10)|BIT(14))); in Hal_XC_SetOffLineToHDMI()
329 W2BYTEMSK(REG_PM_SLP_BASE+0x96,0,(BIT(3)|BIT(7)|BIT(11)|BIT(15))); in Hal_XC_SetOffLineToHDMI()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_xc_chip_config.h382 #define REG_PM_SLP_BASE 0x000E00 macro
383 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung
638 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96)
639 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42)
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_xc_chip_config.h382 #define REG_PM_SLP_BASE 0x000E00 macro
383 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung
638 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96)
639 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42)
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_xc_chip_config.h461 #define REG_PM_SLP_BASE 0x000E00UL macro
463 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung
752 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96)
753 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42)
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_xc_chip_config.h459 #define REG_PM_SLP_BASE 0x000E00UL macro
461 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung
750 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96)
751 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42)
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h478 #define REG_PM_SLP_BASE 0x000E00 macro
481 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung
933 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96)
934 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42)
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h484 #define REG_PM_SLP_BASE 0x000E00 macro
487 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung
939 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96)
940 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42)
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h484 #define REG_PM_SLP_BASE 0x000E00 macro
487 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung
932 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96)
933 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42)
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h486 #define REG_PM_SLP_BASE 0x000E00 macro
489 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung
926 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96)
927 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42)
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h443 #define REG_PM_SLP_BASE 0x000E00UL macro
445 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung
805 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96)
806 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42)
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h531 #define REG_PM_SLP_BASE 0x000E00UL macro
533 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung
912 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96)
913 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42)
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h499 #define REG_PM_SLP_BASE 0x000E00UL macro
501 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung
873 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96)
874 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42)
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h544 #define REG_PM_SLP_BASE 0x000E00UL macro
546 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung
924 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96)
925 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42)
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h486 #define REG_PM_SLP_BASE 0x000E00UL macro
488 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung
859 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96)
860 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42)
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h549 #define REG_PM_SLP_BASE 0x000E00UL macro
551 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung
929 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96)
930 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42)

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