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Searched refs:REG_PM_SLEEP_4B_L (Results 1 – 25 of 34) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhalMHL.c735 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
740 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
745 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(8), BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
759 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(9));// clock R-term in _mhal_mhl_RxRtermControl()
764 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(9));// clock R-term in _mhal_mhl_RxRtermControl()
769 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(9), BIT(9));// clock R-term in _mhal_mhl_RxRtermControl()
783 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(11));// clock R-term in _mhal_mhl_RxRtermControl()
788 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(11));// clock R-term in _mhal_mhl_RxRtermControl()
793 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(11), BIT(11));// clock R-term in _mhal_mhl_RxRtermControl()
807 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(10));// clock R-term in _mhal_mhl_RxRtermControl()
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhalMHL.c735 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
740 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
745 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(8), BIT(8));// clock R-term in _mhal_mhl_RxRtermControl()
759 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(9));// clock R-term in _mhal_mhl_RxRtermControl()
764 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(9));// clock R-term in _mhal_mhl_RxRtermControl()
769 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(9), BIT(9));// clock R-term in _mhal_mhl_RxRtermControl()
783 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(11));// clock R-term in _mhal_mhl_RxRtermControl()
788 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(11));// clock R-term in _mhal_mhl_RxRtermControl()
793 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(11), BIT(11));// clock R-term in _mhal_mhl_RxRtermControl()
807 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(10));// clock R-term in _mhal_mhl_RxRtermControl()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_mux.c385 … PM_W2BYTE(REG_PM_SLEEP_4B_L, 0xE0EE, 0xF0FF); // [15:12]: PD_BG, [7:4]: PD_CLKIN, [3:0]: PD_IBGREX in Hal_SC_mux_set_dvi_mux()
418 … PM_W2BYTE(REG_PM_SLEEP_4B_L, 0xD0DD, 0xF0FF); // [15:12]: PD_BG, [7:4]: PD_CLKIN, [3:0]: PD_IBGREX in Hal_SC_mux_set_dvi_mux()
451 … PM_W2BYTE(REG_PM_SLEEP_4B_L, 0xB0BB, 0xF0FF); // [15:12]: PD_BG, [7:4]: PD_CLKIN, [3:0]: PD_IBGREX in Hal_SC_mux_set_dvi_mux()
484 … PM_W2BYTE(REG_PM_SLEEP_4B_L, 0x7077, 0xF0FF); // [15:12]: PD_BG, [7:4]: PD_CLKIN, [3:0]: PD_IBGREX in Hal_SC_mux_set_dvi_mux()
517 … PM_W2BYTE(REG_PM_SLEEP_4B_L, 0xF0FF, 0xF0FF); // [15:12]: PD_BG, [7:4]: PD_CLKIN, [3:0]: PD_IBGREX in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c1094 PM_W2BYTE(REG_PM_SLEEP_4B_L, 0x0000, 0x00FF); // DVI clock power on //Fix Coverity issue. in Hal_HDMI_init()
1095 PM_W2BYTE(REG_PM_SLEEP_4B_L, 0x0000, 0xFF00); // DVI clock power on //Fix Coverity issue. in Hal_HDMI_init()
1144 PM_W2BYTE(REG_PM_SLEEP_4B_L, 0x0000, 0xFFFF); // DVI clock power on in Hal_HDMI_init()
2526 PM_W2BYTE(REG_PM_SLEEP_4B_L, FALSE ? BMASK(11:8) : 0, BMASK(11:8)); in Hal_DVI_ClkPullLow()
2533 PM_W2BYTE(REG_PM_SLEEP_4B_L, bPullLow ? BIT(8) : 0, BMASK(8:8)); in Hal_DVI_ClkPullLow()
2536 PM_W2BYTE(REG_PM_SLEEP_4B_L, bPullLow ? BIT(9) : 0, BMASK(9:9)); in Hal_DVI_ClkPullLow()
2539 PM_W2BYTE(REG_PM_SLEEP_4B_L, bPullLow ? BIT(10) : 0, BMASK(10:10)); in Hal_DVI_ClkPullLow()
2542 PM_W2BYTE(REG_PM_SLEEP_4B_L, bPullLow ? BIT(11) : 0, BMASK(11:11)); in Hal_DVI_ClkPullLow()
2545 PM_W2BYTE(REG_PM_SLEEP_4B_L, bPullLow ? BMASK(11:8) : 0, BMASK(11:8)); in Hal_DVI_ClkPullLow()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_mux.c385 … PM_W2BYTE(REG_PM_SLEEP_4B_L, 0xE0EE, 0xF0FF); // [15:12]: PD_BG, [7:4]: PD_CLKIN, [3:0]: PD_IBGREX in Hal_SC_mux_set_dvi_mux()
418 … PM_W2BYTE(REG_PM_SLEEP_4B_L, 0xD0DD, 0xF0FF); // [15:12]: PD_BG, [7:4]: PD_CLKIN, [3:0]: PD_IBGREX in Hal_SC_mux_set_dvi_mux()
451 … PM_W2BYTE(REG_PM_SLEEP_4B_L, 0xB0BB, 0xF0FF); // [15:12]: PD_BG, [7:4]: PD_CLKIN, [3:0]: PD_IBGREX in Hal_SC_mux_set_dvi_mux()
484 … PM_W2BYTE(REG_PM_SLEEP_4B_L, 0x7077, 0xF0FF); // [15:12]: PD_BG, [7:4]: PD_CLKIN, [3:0]: PD_IBGREX in Hal_SC_mux_set_dvi_mux()
517 … PM_W2BYTE(REG_PM_SLEEP_4B_L, 0xF0FF, 0xF0FF); // [15:12]: PD_BG, [7:4]: PD_CLKIN, [3:0]: PD_IBGREX in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c1094 PM_W2BYTE(REG_PM_SLEEP_4B_L, 0x0000, 0x00FF); // DVI clock power on //Fix Coverity issue. in Hal_HDMI_init()
1095 PM_W2BYTE(REG_PM_SLEEP_4B_L, 0x0000, 0xFF00); // DVI clock power on //Fix Coverity issue. in Hal_HDMI_init()
1144 PM_W2BYTE(REG_PM_SLEEP_4B_L, 0x0000, 0xFFFF); // DVI clock power on in Hal_HDMI_init()
2526 PM_W2BYTE(REG_PM_SLEEP_4B_L, FALSE ? BMASK(11:8) : 0, BMASK(11:8)); in Hal_DVI_ClkPullLow()
2533 PM_W2BYTE(REG_PM_SLEEP_4B_L, bPullLow ? BIT(8) : 0, BMASK(8:8)); in Hal_DVI_ClkPullLow()
2536 PM_W2BYTE(REG_PM_SLEEP_4B_L, bPullLow ? BIT(9) : 0, BMASK(9:9)); in Hal_DVI_ClkPullLow()
2539 PM_W2BYTE(REG_PM_SLEEP_4B_L, bPullLow ? BIT(10) : 0, BMASK(10:10)); in Hal_DVI_ClkPullLow()
2542 PM_W2BYTE(REG_PM_SLEEP_4B_L, bPullLow ? BIT(11) : 0, BMASK(11:11)); in Hal_DVI_ClkPullLow()
2545 PM_W2BYTE(REG_PM_SLEEP_4B_L, bPullLow ? BMASK(11:8) : 0, BMASK(11:8)); in Hal_DVI_ClkPullLow()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_pm_sleep.h251 #define REG_PM_SLEEP_4B_L (REG_PM_SLEEP_BASE + 0x96) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_pm_sleep.h252 #define REG_PM_SLEEP_4B_L (REG_PM_SLEEP_BASE + 0x96) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_pm_sleep.h252 #define REG_PM_SLEEP_4B_L (REG_PM_SLEEP_BASE + 0x96) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_pm_sleep.h251 #define REG_PM_SLEEP_4B_L (REG_PM_SLEEP_BASE + 0x96) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_pm_sleep.h251 #define REG_PM_SLEEP_4B_L (REG_PM_SLEEP_BASE + 0x96) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_pm_sleep.h251 #define REG_PM_SLEEP_4B_L (REG_PM_SLEEP_BASE + 0x96) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_pm_sleep.h252 #define REG_PM_SLEEP_4B_L (REG_PM_SLEEP_BASE + 0x96) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_pm_sleep.h251 #define REG_PM_SLEEP_4B_L (REG_PM_SLEEP_BASE + 0x96) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_pm_sleep.h251 #define REG_PM_SLEEP_4B_L (REG_PM_SLEEP_BASE + 0x96) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_pm_sleep.h252 #define REG_PM_SLEEP_4B_L (REG_PM_SLEEP_BASE + 0x96) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_pm_sleep.h252 #define REG_PM_SLEEP_4B_L (REG_PM_SLEEP_BASE + 0x96) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_pm_sleep.h251 #define REG_PM_SLEEP_4B_L (REG_PM_SLEEP_BASE + 0x96) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_pm_sleep.h252 #define REG_PM_SLEEP_4B_L (REG_PM_SLEEP_BASE + 0x96) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_pm_sleep.h251 #define REG_PM_SLEEP_4B_L (REG_PM_SLEEP_BASE + 0x96) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_pm_sleep.h251 #define REG_PM_SLEEP_4B_L (REG_PM_SLEEP_BASE + 0x96) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c2997 PM_W2BYTE(REG_PM_SLEEP_4B_L, FALSE ? BMASK(11:8) : 0, BMASK(11:8)); in Hal_DVI_ClkPullLow()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c3734 PM_W2BYTE(REG_PM_SLEEP_4B_L, FALSE ? BMASK(11:8) : 0, BMASK(11:8)); in Hal_DVI_ClkPullLow()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c5344 PM_W2BYTE(REG_PM_SLEEP_4B_L, FALSE ? BMASK(11:8) : 0, BMASK(11:8)); in Hal_DVI_ClkPullLow()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c5444 PM_W2BYTE(REG_PM_SLEEP_4B_L, FALSE ? BMASK(11:8) : 0, BMASK(11:8)); in Hal_DVI_ClkPullLow()

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