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Searched refs:REG_MOD_BK00_44_L (Results 1 – 10 of 10) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/curry/pnl/
H A DhalPNL.c623 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, 0x3FF, 0x3FF); // TTL skew in MHal_PNL_SetOutputType()
677 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, 0x000, 0x3FF); // TTL skew in MHal_PNL_SetOutputType()
749 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, (pstPanelInitData->eLPLL_Mode << 12) , BIT(12)); in MHal_PNL_Init_MOD()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/pnl/
H A DhalPNL.c623 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, 0x3FF, 0x3FF); // TTL skew in MHal_PNL_SetOutputType()
677 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, 0x000, 0x3FF); // TTL skew in MHal_PNL_SetOutputType()
749 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, (pstPanelInitData->eLPLL_Mode << 12) , BIT(12)); in MHal_PNL_Init_MOD()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/pnl/
H A DhalPNL.c623 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, 0x3FF, 0x3FF); // TTL skew in MHal_PNL_SetOutputType()
677 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, 0x000, 0x3FF); // TTL skew in MHal_PNL_SetOutputType()
749 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, (pstPanelInitData->eLPLL_Mode << 12) , BIT(12)); in MHal_PNL_Init_MOD()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/pnl/
H A DhalPNL.c623 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, 0x3FF, 0x3FF); // TTL skew in MHal_PNL_SetOutputType()
677 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, 0x000, 0x3FF); // TTL skew in MHal_PNL_SetOutputType()
749 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, (pstPanelInitData->eLPLL_Mode << 12) , BIT(12)); in MHal_PNL_Init_MOD()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A DhalPNL.c1289 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, 0x3FF, 0x3FF); // TTL skew in MHal_PNL_SetOutputType()
1396 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, 0x000, 0x3FF); // TTL skew in MHal_PNL_SetOutputType()
1461 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, (pstPanelInitData->eLPLL_Mode << 12) , BIT(12)); in MHal_PNL_Init_MOD()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A DhalPNL.c1289 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, 0x3FF, 0x3FF); // TTL skew in MHal_PNL_SetOutputType()
1396 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, 0x000, 0x3FF); // TTL skew in MHal_PNL_SetOutputType()
1461 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, (pstPanelInitData->eLPLL_Mode << 12) , BIT(12)); in MHal_PNL_Init_MOD()
/utopia/UTPA2-700.0.x/modules/xc/drv/pnl/
H A DdrvPNL.c772 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, BIT(14), BIT(14)); in MDrv_PNL_SetPanelType()
804 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, 0, BIT(14)); in MDrv_PNL_SetPanelType()
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/
H A Dhwreg_mod.h245 #define REG_MOD_BK00_44_L _PK_L_(0x00, 0x44) macro
/utopia/UTPA2-700.0.x/modules/xc/drv/pnl/include/
H A Dpnl_hwreg_utility2.h1836 #define REG_MOD_BK00_44_L _PK_L_(0x00, 0x44) macro
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmvideo_context.c2438 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, BIT(15), BIT(15)); in MDrv_XC_OSDC_Control()
2470 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, 0, BIT(15)); in MDrv_XC_OSDC_Control()