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Searched refs:REG_MIU_SOURCE_BASE (Results 1 – 4 of 4) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DregHVD_EX.h242 #define REG_MIU_SOURCE_BASE (0x0600) macro
375 #define EVD_REG_MIF_SOURCE_GROUP0 (REG_MIU_SOURCE_BASE + ((0x0078) << 1))
376 #define EVD_REG_MIF_SOURCE_GROUP1 (REG_MIU_SOURCE_BASE + ((0x0079) << 1))
377 #define EVD_REG_MIF_SOURCE_GROUP2 (REG_MIU_SOURCE_BASE + ((0x007A) << 1))
378 #define EVD_REG_MIF_SOURCE_GROUP3 (REG_MIU_SOURCE_BASE + ((0x007B) << 1))
379 #define EVD_REG_MIF_SOURCE_GROUP4 (REG_MIU_SOURCE_BASE + ((0x007C) << 1))
380 #define EVD_REG_MIF_SOURCE_GROUP5 (REG_MIU_SOURCE_BASE + ((0x007B) << 1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/hvd_v3/
H A DregHVD_EX.h233 #define REG_MIU_SOURCE_BASE (0x0600) macro
494 #define EVD_REG_MIF_SOURCE_GROUP0 (REG_MIU_SOURCE_BASE + ((0x0078) << 1))
495 #define EVD_REG_MIF_SOURCE_GROUP1 (REG_MIU_SOURCE_BASE + ((0x0079) << 1))
496 #define EVD_REG_MIF_SOURCE_GROUP2 (REG_MIU_SOURCE_BASE + ((0x007A) << 1))
497 #define EVD_REG_MIF_SOURCE_GROUP3 (REG_MIU_SOURCE_BASE + ((0x007B) << 1))
498 #define EVD_REG_MIF_SOURCE_GROUP4 (REG_MIU_SOURCE_BASE + ((0x007C) << 1))
499 #define EVD_REG_MIF_SOURCE_GROUP5 (REG_MIU_SOURCE_BASE + ((0x007B) << 1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/hvd_v3/
H A DregHVD_EX.h233 #define REG_MIU_SOURCE_BASE (0x0600) macro
494 #define EVD_REG_MIF_SOURCE_GROUP0 (REG_MIU_SOURCE_BASE + ((0x0078) << 1))
495 #define EVD_REG_MIF_SOURCE_GROUP1 (REG_MIU_SOURCE_BASE + ((0x0079) << 1))
496 #define EVD_REG_MIF_SOURCE_GROUP2 (REG_MIU_SOURCE_BASE + ((0x007A) << 1))
497 #define EVD_REG_MIF_SOURCE_GROUP3 (REG_MIU_SOURCE_BASE + ((0x007B) << 1))
498 #define EVD_REG_MIF_SOURCE_GROUP4 (REG_MIU_SOURCE_BASE + ((0x007C) << 1))
499 #define EVD_REG_MIF_SOURCE_GROUP5 (REG_MIU_SOURCE_BASE + ((0x007B) << 1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/hvd_v3/
H A DregHVD_EX.h233 #define REG_MIU_SOURCE_BASE (0x0600) macro
494 #define EVD_REG_MIF_SOURCE_GROUP0 (REG_MIU_SOURCE_BASE + ((0x0078) << 1))
495 #define EVD_REG_MIF_SOURCE_GROUP1 (REG_MIU_SOURCE_BASE + ((0x0079) << 1))
496 #define EVD_REG_MIF_SOURCE_GROUP2 (REG_MIU_SOURCE_BASE + ((0x007A) << 1))
497 #define EVD_REG_MIF_SOURCE_GROUP3 (REG_MIU_SOURCE_BASE + ((0x007B) << 1))
498 #define EVD_REG_MIF_SOURCE_GROUP4 (REG_MIU_SOURCE_BASE + ((0x007C) << 1))
499 #define EVD_REG_MIF_SOURCE_GROUP5 (REG_MIU_SOURCE_BASE + ((0x007B) << 1))