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Searched refs:REG_MHL_ECBUS_PHY_71 (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhwregMHL.h625 #define REG_MHL_ECBUS_PHY_71 (REG_MHL_ECBUS_PHY_BANK + 0xE2) macro
H A DhalMHL.c1495 …W2BYTEMSK(REG_MHL_ECBUS_PHY_71, 0x0C04, BMASK(15:0)); // [15:8]:reg_crlock_thr, the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/
H A DhwregMHL.h625 #define REG_MHL_ECBUS_PHY_71 (REG_MHL_ECBUS_PHY_BANK + 0xE2) macro
H A DhalMHL.c1173 …W2BYTEMSK(REG_MHL_ECBUS_PHY_71, 0x0C04, BMASK(15:0)); // [15:8]:reg_crlock_thr, the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhwregMHL.h625 #define REG_MHL_ECBUS_PHY_71 (REG_MHL_ECBUS_PHY_BANK + 0xE2) macro
H A DhalMHL.c1441 …W2BYTEMSK(REG_MHL_ECBUS_PHY_71, 0x0C04, BMASK(15:0)); // [15:8]:reg_crlock_thr, the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/
H A DhwregMHL.h625 #define REG_MHL_ECBUS_PHY_71 (REG_MHL_ECBUS_PHY_BANK + 0xE2) macro
H A DhalMHL.c1173 …W2BYTEMSK(REG_MHL_ECBUS_PHY_71, 0x0C04, BMASK(15:0)); // [15:8]:reg_crlock_thr, the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhwregMHL.h625 #define REG_MHL_ECBUS_PHY_71 (REG_MHL_ECBUS_PHY_BANK + 0xE2) macro
H A DhalMHL.c1441 …W2BYTEMSK(REG_MHL_ECBUS_PHY_71, 0x0C04, BMASK(15:0)); // [15:8]:reg_crlock_thr, the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhwregMHL.h625 #define REG_MHL_ECBUS_PHY_71 (REG_MHL_ECBUS_PHY_BANK + 0xE2) macro
H A DhalMHL.c1479 …W2BYTEMSK(REG_MHL_ECBUS_PHY_71, 0x0C04, BMASK(15:0)); // [15:8]:reg_crlock_thr, the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhwregMHL.h625 #define REG_MHL_ECBUS_PHY_71 (REG_MHL_ECBUS_PHY_BANK + 0xE2) macro
H A DhalMHL.c1441 …W2BYTEMSK(REG_MHL_ECBUS_PHY_71, 0x0C04, BMASK(15:0)); // [15:8]:reg_crlock_thr, the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhwregMHL.h625 #define REG_MHL_ECBUS_PHY_71 (REG_MHL_ECBUS_PHY_BANK + 0xE2) macro
H A DhalMHL.c1441 …W2BYTEMSK(REG_MHL_ECBUS_PHY_71, 0x0C04, BMASK(15:0)); // [15:8]:reg_crlock_thr, the CR lock refere… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhwregMHL.h625 #define REG_MHL_ECBUS_PHY_71 (REG_MHL_ECBUS_PHY_BANK + 0xE2) macro
H A DhalMHL.c1441 …W2BYTEMSK(REG_MHL_ECBUS_PHY_71, 0x0C04, BMASK(15:0)); // [15:8]:reg_crlock_thr, the CR lock refere… in _mhal_mhl_ECbusInitialSetting()