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Searched refs:REG_MHL_ECBUS_PHY_6A (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhwregMHL.h618 #define REG_MHL_ECBUS_PHY_6A (REG_MHL_ECBUS_PHY_BANK + 0xD4) macro
H A DhalMHL.c1504 …W2BYTEMSK(REG_MHL_ECBUS_PHY_6A, 0xf117, BMASK(15:0)); // [15:12]:reg_txloc_lck_thr, [10:8]:reg_txl… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/
H A DhwregMHL.h618 #define REG_MHL_ECBUS_PHY_6A (REG_MHL_ECBUS_PHY_BANK + 0xD4) macro
H A DhalMHL.c1182 …W2BYTEMSK(REG_MHL_ECBUS_PHY_6A, 0xf117, BMASK(15:0)); // [15:12]:reg_txloc_lck_thr, [10:8]:reg_txl… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhwregMHL.h618 #define REG_MHL_ECBUS_PHY_6A (REG_MHL_ECBUS_PHY_BANK + 0xD4) macro
H A DhalMHL.c1450 …W2BYTEMSK(REG_MHL_ECBUS_PHY_6A, 0xf117, BMASK(15:0)); // [15:12]:reg_txloc_lck_thr, [10:8]:reg_txl… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/
H A DhwregMHL.h618 #define REG_MHL_ECBUS_PHY_6A (REG_MHL_ECBUS_PHY_BANK + 0xD4) macro
H A DhalMHL.c1182 …W2BYTEMSK(REG_MHL_ECBUS_PHY_6A, 0xf117, BMASK(15:0)); // [15:12]:reg_txloc_lck_thr, [10:8]:reg_txl… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhwregMHL.h618 #define REG_MHL_ECBUS_PHY_6A (REG_MHL_ECBUS_PHY_BANK + 0xD4) macro
H A DhalMHL.c1450 …W2BYTEMSK(REG_MHL_ECBUS_PHY_6A, 0xf117, BMASK(15:0)); // [15:12]:reg_txloc_lck_thr, [10:8]:reg_txl… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhwregMHL.h618 #define REG_MHL_ECBUS_PHY_6A (REG_MHL_ECBUS_PHY_BANK + 0xD4) macro
H A DhalMHL.c1488 …W2BYTEMSK(REG_MHL_ECBUS_PHY_6A, 0xf117, BMASK(15:0)); // [15:12]:reg_txloc_lck_thr, [10:8]:reg_txl… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhwregMHL.h618 #define REG_MHL_ECBUS_PHY_6A (REG_MHL_ECBUS_PHY_BANK + 0xD4) macro
H A DhalMHL.c1450 …W2BYTEMSK(REG_MHL_ECBUS_PHY_6A, 0xf117, BMASK(15:0)); // [15:12]:reg_txloc_lck_thr, [10:8]:reg_txl… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhwregMHL.h618 #define REG_MHL_ECBUS_PHY_6A (REG_MHL_ECBUS_PHY_BANK + 0xD4) macro
H A DhalMHL.c1450 …W2BYTEMSK(REG_MHL_ECBUS_PHY_6A, 0xf117, BMASK(15:0)); // [15:12]:reg_txloc_lck_thr, [10:8]:reg_txl… in _mhal_mhl_ECbusInitialSetting()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhwregMHL.h618 #define REG_MHL_ECBUS_PHY_6A (REG_MHL_ECBUS_PHY_BANK + 0xD4) macro
H A DhalMHL.c1450 …W2BYTEMSK(REG_MHL_ECBUS_PHY_6A, 0xf117, BMASK(15:0)); // [15:12]:reg_txloc_lck_thr, [10:8]:reg_txl… in _mhal_mhl_ECbusInitialSetting()