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Searched refs:REG_MHL_ECBUS_21 (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/
H A DhalMHL.c1554 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(15), BIT(15)); in _mhal_mhl_InsertSRAMSendEMSCData()
1556 while((R2BYTE(REG_MHL_ECBUS_21) & BIT(14)) == BIT(14)); in _mhal_mhl_InsertSRAMSendEMSCData()
4011 W2BYTEMSK(REG_MHL_ECBUS_21, 0, BMASK(9:0)); // SRAM address set 0 in mhal_mhl_InsertEMSCSendData()
4012 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(13), BIT(13)); // Trigger address in mhal_mhl_InsertEMSCSendData()
H A DhwregMHL.h413 #define REG_MHL_ECBUS_21 (REG_MHL_ECBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/
H A DhalMHL.c1554 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(15), BIT(15)); in _mhal_mhl_InsertSRAMSendEMSCData()
1556 while((R2BYTE(REG_MHL_ECBUS_21) & BIT(14)) == BIT(14)); in _mhal_mhl_InsertSRAMSendEMSCData()
4011 W2BYTEMSK(REG_MHL_ECBUS_21, 0, BMASK(9:0)); // SRAM address set 0 in mhal_mhl_InsertEMSCSendData()
4012 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(13), BIT(13)); // Trigger address in mhal_mhl_InsertEMSCSendData()
H A DhwregMHL.h413 #define REG_MHL_ECBUS_21 (REG_MHL_ECBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhalMHL.c1866 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(15), BIT(15)); in _mhal_mhl_InsertSRAMSendEMSCData()
1868 while((R2BYTE(REG_MHL_ECBUS_21) & BIT(14)) == BIT(14)); in _mhal_mhl_InsertSRAMSendEMSCData()
4453 W2BYTEMSK(REG_MHL_ECBUS_21, 0, BMASK(9:0)); // SRAM address set 0 in mhal_mhl_InsertEMSCSendData()
4454 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(13), BIT(13)); // Trigger address in mhal_mhl_InsertEMSCSendData()
H A DhwregMHL.h413 #define REG_MHL_ECBUS_21 (REG_MHL_ECBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhalMHL.c1882 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(15), BIT(15)); in _mhal_mhl_InsertSRAMSendEMSCData()
1884 while((R2BYTE(REG_MHL_ECBUS_21) & BIT(14)) == BIT(14)); in _mhal_mhl_InsertSRAMSendEMSCData()
4477 W2BYTEMSK(REG_MHL_ECBUS_21, 0, BMASK(9:0)); // SRAM address set 0 in mhal_mhl_InsertEMSCSendData()
4478 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(13), BIT(13)); // Trigger address in mhal_mhl_InsertEMSCSendData()
H A DhwregMHL.h413 #define REG_MHL_ECBUS_21 (REG_MHL_ECBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhalMHL.c1895 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(15), BIT(15)); in _mhal_mhl_InsertSRAMSendEMSCData()
1897 while((R2BYTE(REG_MHL_ECBUS_21) & BIT(14)) == BIT(14)); in _mhal_mhl_InsertSRAMSendEMSCData()
5065 W2BYTEMSK(REG_MHL_ECBUS_21, 0, BMASK(9:0)); // SRAM address set 0 in mhal_mhl_InsertEMSCSendData()
5066 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(13), BIT(13)); // Trigger address in mhal_mhl_InsertEMSCSendData()
H A DhwregMHL.h413 #define REG_MHL_ECBUS_21 (REG_MHL_ECBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhalMHL.c1895 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(15), BIT(15)); in _mhal_mhl_InsertSRAMSendEMSCData()
1897 while((R2BYTE(REG_MHL_ECBUS_21) & BIT(14)) == BIT(14)); in _mhal_mhl_InsertSRAMSendEMSCData()
5065 W2BYTEMSK(REG_MHL_ECBUS_21, 0, BMASK(9:0)); // SRAM address set 0 in mhal_mhl_InsertEMSCSendData()
5066 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(13), BIT(13)); // Trigger address in mhal_mhl_InsertEMSCSendData()
H A DhwregMHL.h413 #define REG_MHL_ECBUS_21 (REG_MHL_ECBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhalMHL.c1895 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(15), BIT(15)); in _mhal_mhl_InsertSRAMSendEMSCData()
1897 while((R2BYTE(REG_MHL_ECBUS_21) & BIT(14)) == BIT(14)); in _mhal_mhl_InsertSRAMSendEMSCData()
5065 W2BYTEMSK(REG_MHL_ECBUS_21, 0, BMASK(9:0)); // SRAM address set 0 in mhal_mhl_InsertEMSCSendData()
5066 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(13), BIT(13)); // Trigger address in mhal_mhl_InsertEMSCSendData()
H A DhwregMHL.h413 #define REG_MHL_ECBUS_21 (REG_MHL_ECBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhalMHL.c1895 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(15), BIT(15)); in _mhal_mhl_InsertSRAMSendEMSCData()
1897 while((R2BYTE(REG_MHL_ECBUS_21) & BIT(14)) == BIT(14)); in _mhal_mhl_InsertSRAMSendEMSCData()
5065 W2BYTEMSK(REG_MHL_ECBUS_21, 0, BMASK(9:0)); // SRAM address set 0 in mhal_mhl_InsertEMSCSendData()
5066 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(13), BIT(13)); // Trigger address in mhal_mhl_InsertEMSCSendData()
H A DhwregMHL.h413 #define REG_MHL_ECBUS_21 (REG_MHL_ECBUS_BANK + 0x42) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhalMHL.c1895 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(15), BIT(15)); in _mhal_mhl_InsertSRAMSendEMSCData()
1897 while((R2BYTE(REG_MHL_ECBUS_21) & BIT(14)) == BIT(14)); in _mhal_mhl_InsertSRAMSendEMSCData()
5065 W2BYTEMSK(REG_MHL_ECBUS_21, 0, BMASK(9:0)); // SRAM address set 0 in mhal_mhl_InsertEMSCSendData()
5066 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(13), BIT(13)); // Trigger address in mhal_mhl_InsertEMSCSendData()
H A DhwregMHL.h413 #define REG_MHL_ECBUS_21 (REG_MHL_ECBUS_BANK + 0x42) macro