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Searched refs:REG_HDMI2_BASE (Results 1 – 25 of 46) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h1214 #define REG_HDMI2_01_L (REG_HDMI2_BASE + 0x02)
1215 #define REG_HDMI2_01_H (REG_HDMI2_BASE + 0x03)
1216 #define REG_HDMI2_02_L (REG_HDMI2_BASE + 0x04)
1217 #define REG_HDMI2_02_H (REG_HDMI2_BASE + 0x05)
1218 #define REG_HDMI2_03_L (REG_HDMI2_BASE + 0x06)
1219 #define REG_HDMI2_03_H (REG_HDMI2_BASE + 0x07)
1220 #define REG_HDMI2_06_L (REG_HDMI2_BASE + 0x0C)
1221 #define REG_HDMI2_06_H (REG_HDMI2_BASE + 0x0D)
1222 #define REG_HDMI2_08_L (REG_HDMI2_BASE + 0x10)
1223 #define REG_HDMI2_08_H (REG_HDMI2_BASE + 0x11)
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/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h1214 #define REG_HDMI2_01_L (REG_HDMI2_BASE + 0x02)
1215 #define REG_HDMI2_01_H (REG_HDMI2_BASE + 0x03)
1216 #define REG_HDMI2_02_L (REG_HDMI2_BASE + 0x04)
1217 #define REG_HDMI2_02_H (REG_HDMI2_BASE + 0x05)
1218 #define REG_HDMI2_03_L (REG_HDMI2_BASE + 0x06)
1219 #define REG_HDMI2_03_H (REG_HDMI2_BASE + 0x07)
1220 #define REG_HDMI2_06_L (REG_HDMI2_BASE + 0x0C)
1221 #define REG_HDMI2_06_H (REG_HDMI2_BASE + 0x0D)
1222 #define REG_HDMI2_08_L (REG_HDMI2_BASE + 0x10)
1223 #define REG_HDMI2_08_H (REG_HDMI2_BASE + 0x11)
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/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/cec/include/
H A Dcec_hwreg.h120 #define REG_HDMI2_BASE 0x101A00UL macro
173 #define REG_HDMI2_26_L (REG_HDMI2_BASE + 0x4C)
174 #define REG_HDMI2_26_H (REG_HDMI2_BASE + 0x4D)
175 #define REG_HDMI2_27_L (REG_HDMI2_BASE + 0x4E)
176 #define REG_HDMI2_27_H (REG_HDMI2_BASE + 0x4F)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/cec/include/
H A Dcec_hwreg.h120 #define REG_HDMI2_BASE 0x101A00UL macro
173 #define REG_HDMI2_26_L (REG_HDMI2_BASE + 0x4C)
174 #define REG_HDMI2_26_H (REG_HDMI2_BASE + 0x4D)
175 #define REG_HDMI2_27_L (REG_HDMI2_BASE + 0x4E)
176 #define REG_HDMI2_27_H (REG_HDMI2_BASE + 0x4F)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/cec/include/
H A Dcec_hwreg.h120 #define REG_HDMI2_BASE 0x101A00UL macro
173 #define REG_HDMI2_26_L (REG_HDMI2_BASE + 0x4C)
174 #define REG_HDMI2_26_H (REG_HDMI2_BASE + 0x4D)
175 #define REG_HDMI2_27_L (REG_HDMI2_BASE + 0x4E)
176 #define REG_HDMI2_27_H (REG_HDMI2_BASE + 0x4F)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/cec/include/
H A Dcec_hwreg.h120 #define REG_HDMI2_BASE 0x101A00 macro
170 #define REG_HDMI2_26_L (REG_HDMI2_BASE + 0x4C)
171 #define REG_HDMI2_26_H (REG_HDMI2_BASE + 0x4D)
172 #define REG_HDMI2_27_L (REG_HDMI2_BASE + 0x4E)
173 #define REG_HDMI2_27_H (REG_HDMI2_BASE + 0x4F)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/cec/include/
H A Dcec_hwreg.h120 #define REG_HDMI2_BASE 0x101A00UL macro
173 #define REG_HDMI2_26_L (REG_HDMI2_BASE + 0x4C)
174 #define REG_HDMI2_26_H (REG_HDMI2_BASE + 0x4D)
175 #define REG_HDMI2_27_L (REG_HDMI2_BASE + 0x4E)
176 #define REG_HDMI2_27_H (REG_HDMI2_BASE + 0x4F)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/cec/include/
H A Dcec_hwreg.h120 #define REG_HDMI2_BASE 0x101A00UL macro
173 #define REG_HDMI2_26_L (REG_HDMI2_BASE + 0x4C)
174 #define REG_HDMI2_26_H (REG_HDMI2_BASE + 0x4D)
175 #define REG_HDMI2_27_L (REG_HDMI2_BASE + 0x4E)
176 #define REG_HDMI2_27_H (REG_HDMI2_BASE + 0x4F)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/cec/include/
H A Dcec_hwreg.h120 #define REG_HDMI2_BASE 0x101A00UL macro
173 #define REG_HDMI2_26_L (REG_HDMI2_BASE + 0x4C)
174 #define REG_HDMI2_26_H (REG_HDMI2_BASE + 0x4D)
175 #define REG_HDMI2_27_L (REG_HDMI2_BASE + 0x4E)
176 #define REG_HDMI2_27_H (REG_HDMI2_BASE + 0x4F)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/cec/include/
H A Dcec_hwreg.h120 #define REG_HDMI2_BASE 0x101A00UL macro
173 #define REG_HDMI2_26_L (REG_HDMI2_BASE + 0x4C)
174 #define REG_HDMI2_26_H (REG_HDMI2_BASE + 0x4D)
175 #define REG_HDMI2_27_L (REG_HDMI2_BASE + 0x4E)
176 #define REG_HDMI2_27_H (REG_HDMI2_BASE + 0x4F)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/cec/include/
H A Dcec_hwreg.h120 #define REG_HDMI2_BASE 0x101A00UL macro
173 #define REG_HDMI2_26_L (REG_HDMI2_BASE + 0x4C)
174 #define REG_HDMI2_26_H (REG_HDMI2_BASE + 0x4D)
175 #define REG_HDMI2_27_L (REG_HDMI2_BASE + 0x4E)
176 #define REG_HDMI2_27_H (REG_HDMI2_BASE + 0x4F)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/cec/include/
H A Dcec_hwreg.h120 #define REG_HDMI2_BASE 0x101A00 macro
170 #define REG_HDMI2_26_L (REG_HDMI2_BASE + 0x4C)
171 #define REG_HDMI2_26_H (REG_HDMI2_BASE + 0x4D)
172 #define REG_HDMI2_27_L (REG_HDMI2_BASE + 0x4E)
173 #define REG_HDMI2_27_H (REG_HDMI2_BASE + 0x4F)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/cec/include/
H A Dcec_hwreg.h120 #define REG_HDMI2_BASE 0x101A00UL macro
173 #define REG_HDMI2_26_L (REG_HDMI2_BASE + 0x4C)
174 #define REG_HDMI2_26_H (REG_HDMI2_BASE + 0x4D)
175 #define REG_HDMI2_27_L (REG_HDMI2_BASE + 0x4E)
176 #define REG_HDMI2_27_H (REG_HDMI2_BASE + 0x4F)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/cec/include/
H A Dcec_hwreg.h120 #define REG_HDMI2_BASE 0x101A00UL macro
173 #define REG_HDMI2_26_L (REG_HDMI2_BASE + 0x4C)
174 #define REG_HDMI2_26_H (REG_HDMI2_BASE + 0x4D)
175 #define REG_HDMI2_27_L (REG_HDMI2_BASE + 0x4E)
176 #define REG_HDMI2_27_H (REG_HDMI2_BASE + 0x4F)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/cec/include/
H A Dcec_hwreg.h120 #define REG_HDMI2_BASE 0x101A00UL macro
173 #define REG_HDMI2_26_L (REG_HDMI2_BASE + 0x4C)
174 #define REG_HDMI2_26_H (REG_HDMI2_BASE + 0x4D)
175 #define REG_HDMI2_27_L (REG_HDMI2_BASE + 0x4E)
176 #define REG_HDMI2_27_H (REG_HDMI2_BASE + 0x4F)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/cec/include/
H A Dcec_hwreg.h120 #define REG_HDMI2_BASE 0x101A00UL macro
173 #define REG_HDMI2_26_L (REG_HDMI2_BASE + 0x4C)
174 #define REG_HDMI2_26_H (REG_HDMI2_BASE + 0x4D)
175 #define REG_HDMI2_27_L (REG_HDMI2_BASE + 0x4E)
176 #define REG_HDMI2_27_H (REG_HDMI2_BASE + 0x4F)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/cec/include/
H A Dcec_hwreg.h120 #define REG_HDMI2_BASE 0x101A00UL macro
173 #define REG_HDMI2_26_L (REG_HDMI2_BASE + 0x4C)
174 #define REG_HDMI2_26_H (REG_HDMI2_BASE + 0x4D)
175 #define REG_HDMI2_27_L (REG_HDMI2_BASE + 0x4E)
176 #define REG_HDMI2_27_H (REG_HDMI2_BASE + 0x4F)
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h1196 #define REG_HDMI2_01_L (REG_HDMI2_BASE + 0x02)
1197 #define REG_HDMI2_01_H (REG_HDMI2_BASE + 0x03)
1198 #define REG_HDMI2_02_L (REG_HDMI2_BASE + 0x04)
1199 #define REG_HDMI2_02_H (REG_HDMI2_BASE + 0x05)
1200 #define REG_HDMI2_03_L (REG_HDMI2_BASE + 0x06)
1201 #define REG_HDMI2_03_H (REG_HDMI2_BASE + 0x07)
1202 #define REG_HDMI2_06_L (REG_HDMI2_BASE + 0x0C)
1203 #define REG_HDMI2_06_H (REG_HDMI2_BASE + 0x0D)
1204 #define REG_HDMI2_08_L (REG_HDMI2_BASE + 0x10)
1205 #define REG_HDMI2_08_H (REG_HDMI2_BASE + 0x11)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h1196 #define REG_HDMI2_01_L (REG_HDMI2_BASE + 0x02)
1197 #define REG_HDMI2_01_H (REG_HDMI2_BASE + 0x03)
1198 #define REG_HDMI2_02_L (REG_HDMI2_BASE + 0x04)
1199 #define REG_HDMI2_02_H (REG_HDMI2_BASE + 0x05)
1200 #define REG_HDMI2_03_L (REG_HDMI2_BASE + 0x06)
1201 #define REG_HDMI2_03_H (REG_HDMI2_BASE + 0x07)
1202 #define REG_HDMI2_06_L (REG_HDMI2_BASE + 0x0C)
1203 #define REG_HDMI2_06_H (REG_HDMI2_BASE + 0x0D)
1204 #define REG_HDMI2_08_L (REG_HDMI2_BASE + 0x10)
1205 #define REG_HDMI2_08_H (REG_HDMI2_BASE + 0x11)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h1196 #define REG_HDMI2_01_L (REG_HDMI2_BASE + 0x02)
1197 #define REG_HDMI2_01_H (REG_HDMI2_BASE + 0x03)
1198 #define REG_HDMI2_02_L (REG_HDMI2_BASE + 0x04)
1199 #define REG_HDMI2_02_H (REG_HDMI2_BASE + 0x05)
1200 #define REG_HDMI2_03_L (REG_HDMI2_BASE + 0x06)
1201 #define REG_HDMI2_03_H (REG_HDMI2_BASE + 0x07)
1202 #define REG_HDMI2_06_L (REG_HDMI2_BASE + 0x0C)
1203 #define REG_HDMI2_06_H (REG_HDMI2_BASE + 0x0D)
1204 #define REG_HDMI2_08_L (REG_HDMI2_BASE + 0x10)
1205 #define REG_HDMI2_08_H (REG_HDMI2_BASE + 0x11)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h1196 #define REG_HDMI2_01_L (REG_HDMI2_BASE + 0x02)
1197 #define REG_HDMI2_01_H (REG_HDMI2_BASE + 0x03)
1198 #define REG_HDMI2_02_L (REG_HDMI2_BASE + 0x04)
1199 #define REG_HDMI2_02_H (REG_HDMI2_BASE + 0x05)
1200 #define REG_HDMI2_03_L (REG_HDMI2_BASE + 0x06)
1201 #define REG_HDMI2_03_H (REG_HDMI2_BASE + 0x07)
1202 #define REG_HDMI2_06_L (REG_HDMI2_BASE + 0x0C)
1203 #define REG_HDMI2_06_H (REG_HDMI2_BASE + 0x0D)
1204 #define REG_HDMI2_08_L (REG_HDMI2_BASE + 0x10)
1205 #define REG_HDMI2_08_H (REG_HDMI2_BASE + 0x11)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h1196 #define REG_HDMI2_01_L (REG_HDMI2_BASE + 0x02)
1197 #define REG_HDMI2_01_H (REG_HDMI2_BASE + 0x03)
1198 #define REG_HDMI2_02_L (REG_HDMI2_BASE + 0x04)
1199 #define REG_HDMI2_02_H (REG_HDMI2_BASE + 0x05)
1200 #define REG_HDMI2_03_L (REG_HDMI2_BASE + 0x06)
1201 #define REG_HDMI2_03_H (REG_HDMI2_BASE + 0x07)
1202 #define REG_HDMI2_06_L (REG_HDMI2_BASE + 0x0C)
1203 #define REG_HDMI2_06_H (REG_HDMI2_BASE + 0x0D)
1204 #define REG_HDMI2_08_L (REG_HDMI2_BASE + 0x10)
1205 #define REG_HDMI2_08_H (REG_HDMI2_BASE + 0x11)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h1196 #define REG_HDMI2_01_L (REG_HDMI2_BASE + 0x02)
1197 #define REG_HDMI2_01_H (REG_HDMI2_BASE + 0x03)
1198 #define REG_HDMI2_02_L (REG_HDMI2_BASE + 0x04)
1199 #define REG_HDMI2_02_H (REG_HDMI2_BASE + 0x05)
1200 #define REG_HDMI2_03_L (REG_HDMI2_BASE + 0x06)
1201 #define REG_HDMI2_03_H (REG_HDMI2_BASE + 0x07)
1202 #define REG_HDMI2_06_L (REG_HDMI2_BASE + 0x0C)
1203 #define REG_HDMI2_06_H (REG_HDMI2_BASE + 0x0D)
1204 #define REG_HDMI2_08_L (REG_HDMI2_BASE + 0x10)
1205 #define REG_HDMI2_08_H (REG_HDMI2_BASE + 0x11)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h1196 #define REG_HDMI2_01_L (REG_HDMI2_BASE + 0x02)
1197 #define REG_HDMI2_01_H (REG_HDMI2_BASE + 0x03)
1198 #define REG_HDMI2_02_L (REG_HDMI2_BASE + 0x04)
1199 #define REG_HDMI2_02_H (REG_HDMI2_BASE + 0x05)
1200 #define REG_HDMI2_03_L (REG_HDMI2_BASE + 0x06)
1201 #define REG_HDMI2_03_H (REG_HDMI2_BASE + 0x07)
1202 #define REG_HDMI2_06_L (REG_HDMI2_BASE + 0x0C)
1203 #define REG_HDMI2_06_H (REG_HDMI2_BASE + 0x0D)
1204 #define REG_HDMI2_08_L (REG_HDMI2_BASE + 0x10)
1205 #define REG_HDMI2_08_H (REG_HDMI2_BASE + 0x11)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h1196 #define REG_HDMI2_01_L (REG_HDMI2_BASE + 0x02)
1197 #define REG_HDMI2_01_H (REG_HDMI2_BASE + 0x03)
1198 #define REG_HDMI2_02_L (REG_HDMI2_BASE + 0x04)
1199 #define REG_HDMI2_02_H (REG_HDMI2_BASE + 0x05)
1200 #define REG_HDMI2_03_L (REG_HDMI2_BASE + 0x06)
1201 #define REG_HDMI2_03_H (REG_HDMI2_BASE + 0x07)
1202 #define REG_HDMI2_06_L (REG_HDMI2_BASE + 0x0C)
1203 #define REG_HDMI2_06_H (REG_HDMI2_BASE + 0x0D)
1204 #define REG_HDMI2_08_L (REG_HDMI2_BASE + 0x10)
1205 #define REG_HDMI2_08_H (REG_HDMI2_BASE + 0x11)
[all …]

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