| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 1394 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L, 0, BIT(0)); in Hal_HDCP22_PortInit()
1451 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L, bIsEnable? BIT(0): 0, BIT(0)); in Hal_HDCP22_EnableCipher()
1502 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L, BIT(0), BIT(0)); in Hal_HDCP22_FillCipherKey()
2054 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L, BIT(2)|BIT(1), BIT(2)|BIT(1)); in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 2097 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L, 0, BIT(0)); in Hal_HDCP22_PortInit()
2154 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L, bIsEnable? BIT(0): 0, BIT(0)); in Hal_HDCP22_EnableCipher()
2205 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L, BIT(0), BIT(0)); in Hal_HDCP22_FillCipherKey()
2790 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L, BIT(2)|BIT(1), BIT(2)|BIT(1)); in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 3308 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L + dwBKOffset, 0, BIT(0)); in Hal_HDCP22_PortInit()
3377 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L + dwBKOffset, bIsEnable? BIT(0): 0, BIT(0)); in Hal_HDCP22_EnableCipher()
3433 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L + dwBKOffset, BIT(0), BIT(0)); in Hal_HDCP22_FillCipherKey()
4271 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L, BIT(2)|BIT(1), BIT(2)|BIT(1)); in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 3978 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L + dwBKOffset, 0, BIT(0)); in Hal_HDCP22_PortInit()
4047 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L + dwBKOffset, bIsEnable? BIT(0): 0, BIT(0)); in Hal_HDCP22_EnableCipher()
4103 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L + dwBKOffset, BIT(0), BIT(0)); in Hal_HDCP22_FillCipherKey()
4954 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L, BIT(2)|BIT(1), BIT(2)|BIT(1)); in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 3981 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L + dwBKOffset, 0, BIT(0)); in Hal_HDCP22_PortInit()
4050 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L + dwBKOffset, bIsEnable? BIT(0): 0, BIT(0)); in Hal_HDCP22_EnableCipher()
4106 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L + dwBKOffset, BIT(0), BIT(0)); in Hal_HDCP22_FillCipherKey()
4957 W2BYTEMSK(REG_HDCP_DUAL_P0_4E_L, BIT(2)|BIT(1), BIT(2)|BIT(1)); in Hal_HDMI_init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 4043 #define REG_HDCP_DUAL_P0_4E_L (REG_HDCP_DUAL_P0_BASE + 0x9C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 4045 #define REG_HDCP_DUAL_P0_4E_L (REG_HDCP_DUAL_P0_BASE + 0x9C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 4043 #define REG_HDCP_DUAL_P0_4E_L (REG_HDCP_DUAL_P0_BASE + 0x9C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 4045 #define REG_HDCP_DUAL_P0_4E_L (REG_HDCP_DUAL_P0_BASE + 0x9C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 4043 #define REG_HDCP_DUAL_P0_4E_L (REG_HDCP_DUAL_P0_BASE + 0x9C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 4045 #define REG_HDCP_DUAL_P0_4E_L (REG_HDCP_DUAL_P0_BASE + 0x9C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 4045 #define REG_HDCP_DUAL_P0_4E_L (REG_HDCP_DUAL_P0_BASE + 0x9C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 4043 #define REG_HDCP_DUAL_P0_4E_L (REG_HDCP_DUAL_P0_BASE + 0x9C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 4044 #define REG_HDCP_DUAL_P0_4E_L (REG_HDCP_DUAL_P0_BASE + 0x9C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 4043 #define REG_HDCP_DUAL_P0_4E_L (REG_HDCP_DUAL_P0_BASE + 0x9C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 4043 #define REG_HDCP_DUAL_P0_4E_L (REG_HDCP_DUAL_P0_BASE + 0x9C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 4043 #define REG_HDCP_DUAL_P0_4E_L (REG_HDCP_DUAL_P0_BASE + 0x9C) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | hwreg_hdmi.h | 4043 #define REG_HDCP_DUAL_P0_4E_L (REG_HDCP_DUAL_P0_BASE + 0x9C) macro
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