| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 3414 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L, BIT(0)); // DTOP_3E[0]: dvi sw reset in Hal_DVI_Software_Reset()
3415 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L, 0); in Hal_DVI_Software_Reset()
3419 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L, BIT(2)); // DTOP_3E[2]: hdcp sw reset in Hal_DVI_Software_Reset()
3420 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L, 0); in Hal_DVI_Software_Reset()
3424 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L, BIT(3)); // DTOP_3E[3]: hdmi sw reset in Hal_DVI_Software_Reset()
3425 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L, 0); in Hal_DVI_Software_Reset()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_hdmi.c | 4151 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L, BIT(0)); // DTOP_3E[0]: dvi sw reset in Hal_DVI_Software_Reset()
4152 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L, 0); in Hal_DVI_Software_Reset()
4156 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L, BIT(2)); // DTOP_3E[2]: hdcp sw reset in Hal_DVI_Software_Reset()
4157 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L, 0); in Hal_DVI_Software_Reset()
4161 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L, BIT(3)); // DTOP_3E[3]: hdmi sw reset in Hal_DVI_Software_Reset()
4162 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L, 0); in Hal_DVI_Software_Reset()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 5859 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(0)); // DTOP_3E[0]: dvi sw reset in Hal_DVI_Software_Reset()
5860 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
5864 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(2)); // DTOP_3E[2]: hdcp sw reset in Hal_DVI_Software_Reset()
5865 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
5869 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(3)); // DTOP_3E[3]: hdmi sw reset in Hal_DVI_Software_Reset()
5870 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 5927 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(0)); // DTOP_3E[0]: dvi sw reset in Hal_DVI_Software_Reset()
5928 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
5932 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(2)); // DTOP_3E[2]: hdcp sw reset in Hal_DVI_Software_Reset()
5933 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
5937 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(3)); // DTOP_3E[3]: hdmi sw reset in Hal_DVI_Software_Reset()
5938 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 5981 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(0)); // DTOP_3E[0]: dvi sw reset in Hal_DVI_Software_Reset()
5982 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
5986 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(2)); // DTOP_3E[2]: hdcp sw reset in Hal_DVI_Software_Reset()
5987 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
5991 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(3)); // DTOP_3E[3]: hdmi sw reset in Hal_DVI_Software_Reset()
5992 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 5927 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(0)); // DTOP_3E[0]: dvi sw reset in Hal_DVI_Software_Reset()
5928 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
5932 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(2)); // DTOP_3E[2]: hdcp sw reset in Hal_DVI_Software_Reset()
5933 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
5937 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(3)); // DTOP_3E[3]: hdmi sw reset in Hal_DVI_Software_Reset()
5938 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 5974 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(0)); // DTOP_3E[0]: dvi sw reset in Hal_DVI_Software_Reset()
5975 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
5979 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(2)); // DTOP_3E[2]: hdcp sw reset in Hal_DVI_Software_Reset()
5980 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
5984 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(3)); // DTOP_3E[3]: hdmi sw reset in Hal_DVI_Software_Reset()
5985 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 5981 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(0)); // DTOP_3E[0]: dvi sw reset in Hal_DVI_Software_Reset()
5982 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
5986 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(2)); // DTOP_3E[2]: hdcp sw reset in Hal_DVI_Software_Reset()
5987 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
5991 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(3)); // DTOP_3E[3]: hdmi sw reset in Hal_DVI_Software_Reset()
5992 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 6562 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(0)); // DTOP_3E[0]: dvi sw reset in Hal_DVI_Software_Reset()
6563 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
6567 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(2)); // DTOP_3E[2]: hdcp sw reset in Hal_DVI_Software_Reset()
6568 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
6572 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(3)); // DTOP_3E[3]: hdmi sw reset in Hal_DVI_Software_Reset()
6573 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 6565 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(0)); // DTOP_3E[0]: dvi sw reset in Hal_DVI_Software_Reset()
6566 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
6570 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(2)); // DTOP_3E[2]: hdcp sw reset in Hal_DVI_Software_Reset()
6571 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
6575 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(3)); // DTOP_3E[3]: hdmi sw reset in Hal_DVI_Software_Reset()
6576 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 6337 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(0)); // DTOP_3E[0]: dvi sw reset in Hal_DVI_Software_Reset()
6338 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
6342 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(2)); // DTOP_3E[2]: hdcp sw reset in Hal_DVI_Software_Reset()
6343 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
6347 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(3)); // DTOP_3E[3]: hdmi sw reset in Hal_DVI_Software_Reset()
6348 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 6568 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(0)); // DTOP_3E[0]: dvi sw reset in Hal_DVI_Software_Reset()
6569 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
6573 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(2)); // DTOP_3E[2]: hdcp sw reset in Hal_DVI_Software_Reset()
6574 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
6578 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(3)); // DTOP_3E[3]: hdmi sw reset in Hal_DVI_Software_Reset()
6579 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 6337 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(0)); // DTOP_3E[0]: dvi sw reset in Hal_DVI_Software_Reset()
6338 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
6342 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(2)); // DTOP_3E[2]: hdcp sw reset in Hal_DVI_Software_Reset()
6343 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
6347 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, BIT(3)); // DTOP_3E[3]: hdmi sw reset in Hal_DVI_Software_Reset()
6348 W2BYTE(REG_DVI_DTOP_DUAL_P0_3E_L + u16DTOPOffset, 0); in Hal_DVI_Software_Reset()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 3687 #define REG_DVI_DTOP_DUAL_P0_3E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x7C) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 3689 #define REG_DVI_DTOP_DUAL_P0_3E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x7C) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 3687 #define REG_DVI_DTOP_DUAL_P0_3E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x7C) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 3689 #define REG_DVI_DTOP_DUAL_P0_3E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x7C) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 3687 #define REG_DVI_DTOP_DUAL_P0_3E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x7C) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 3689 #define REG_DVI_DTOP_DUAL_P0_3E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x7C) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 3689 #define REG_DVI_DTOP_DUAL_P0_3E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x7C) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 3687 #define REG_DVI_DTOP_DUAL_P0_3E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x7C) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 3688 #define REG_DVI_DTOP_DUAL_P0_3E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x7C) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 3687 #define REG_DVI_DTOP_DUAL_P0_3E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x7C) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 3687 #define REG_DVI_DTOP_DUAL_P0_3E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x7C) macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 3687 #define REG_DVI_DTOP_DUAL_P0_3E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x7C) macro
|