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Searched refs:REG_DVI_ATOP2_BASE (Results 1 – 25 of 46) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdmi.h823 #define REG_DVI_ATOP2_00_L (REG_DVI_ATOP2_BASE + 0x00)
824 #define REG_DVI_ATOP2_00_H (REG_DVI_ATOP2_BASE + 0x01)
825 #define REG_DVI_ATOP2_01_L (REG_DVI_ATOP2_BASE + 0x02)
826 #define REG_DVI_ATOP2_01_H (REG_DVI_ATOP2_BASE + 0x03)
827 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
828 #define REG_DVI_ATOP2_06_H (REG_DVI_ATOP2_BASE + 0x0D)
829 #define REG_DVI_ATOP2_07_L (REG_DVI_ATOP2_BASE + 0x0E) // ENABLE_PATCH_HDCP_FOR_SEC_PC
830 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64)
831 #define REG_DVI_ATOP2_32_H (REG_DVI_ATOP2_BASE + 0x65)
834 #define REG_DVI_ATOP2_5E_L (REG_DVI_ATOP2_BASE + 0xBC)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdmi.h823 #define REG_DVI_ATOP2_00_L (REG_DVI_ATOP2_BASE + 0x00)
824 #define REG_DVI_ATOP2_00_H (REG_DVI_ATOP2_BASE + 0x01)
825 #define REG_DVI_ATOP2_01_L (REG_DVI_ATOP2_BASE + 0x02)
826 #define REG_DVI_ATOP2_01_H (REG_DVI_ATOP2_BASE + 0x03)
827 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
828 #define REG_DVI_ATOP2_06_H (REG_DVI_ATOP2_BASE + 0x0D)
829 #define REG_DVI_ATOP2_07_L (REG_DVI_ATOP2_BASE + 0x0E) // ENABLE_PATCH_HDCP_FOR_SEC_PC
830 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64)
831 #define REG_DVI_ATOP2_32_H (REG_DVI_ATOP2_BASE + 0x65)
834 #define REG_DVI_ATOP2_5E_L (REG_DVI_ATOP2_BASE + 0xBC)
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/cec/include/
H A Dcec_hwreg.h129 #define REG_DVI_ATOP2_BASE 0x113400UL macro
150 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
151 #define REG_DVI_ATOP2_70_H (REG_DVI_ATOP2_BASE + 0xE1)
152 #define REG_DVI_ATOP2_71_H (REG_DVI_ATOP2_BASE + 0xE3)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/cec/include/
H A Dcec_hwreg.h129 #define REG_DVI_ATOP2_BASE 0x113400UL macro
150 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
151 #define REG_DVI_ATOP2_70_H (REG_DVI_ATOP2_BASE + 0xE1)
152 #define REG_DVI_ATOP2_71_H (REG_DVI_ATOP2_BASE + 0xE3)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/cec/include/
H A Dcec_hwreg.h129 #define REG_DVI_ATOP2_BASE 0x113400UL macro
150 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
151 #define REG_DVI_ATOP2_70_H (REG_DVI_ATOP2_BASE + 0xE1)
152 #define REG_DVI_ATOP2_71_H (REG_DVI_ATOP2_BASE + 0xE3)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/cec/include/
H A Dcec_hwreg.h129 #define REG_DVI_ATOP2_BASE 0x113400 macro
147 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
148 #define REG_DVI_ATOP2_70_H (REG_DVI_ATOP2_BASE + 0xE1)
149 #define REG_DVI_ATOP2_71_H (REG_DVI_ATOP2_BASE + 0xE3)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/cec/include/
H A Dcec_hwreg.h129 #define REG_DVI_ATOP2_BASE 0x113400UL macro
150 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
151 #define REG_DVI_ATOP2_70_H (REG_DVI_ATOP2_BASE + 0xE1)
152 #define REG_DVI_ATOP2_71_H (REG_DVI_ATOP2_BASE + 0xE3)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/cec/include/
H A Dcec_hwreg.h129 #define REG_DVI_ATOP2_BASE 0x113400UL macro
150 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
151 #define REG_DVI_ATOP2_70_H (REG_DVI_ATOP2_BASE + 0xE1)
152 #define REG_DVI_ATOP2_71_H (REG_DVI_ATOP2_BASE + 0xE3)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/cec/include/
H A Dcec_hwreg.h129 #define REG_DVI_ATOP2_BASE 0x113400UL macro
150 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
151 #define REG_DVI_ATOP2_70_H (REG_DVI_ATOP2_BASE + 0xE1)
152 #define REG_DVI_ATOP2_71_H (REG_DVI_ATOP2_BASE + 0xE3)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/cec/include/
H A Dcec_hwreg.h129 #define REG_DVI_ATOP2_BASE 0x113400UL macro
150 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
151 #define REG_DVI_ATOP2_70_H (REG_DVI_ATOP2_BASE + 0xE1)
152 #define REG_DVI_ATOP2_71_H (REG_DVI_ATOP2_BASE + 0xE3)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/cec/include/
H A Dcec_hwreg.h129 #define REG_DVI_ATOP2_BASE 0x113400UL macro
150 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
151 #define REG_DVI_ATOP2_70_H (REG_DVI_ATOP2_BASE + 0xE1)
152 #define REG_DVI_ATOP2_71_H (REG_DVI_ATOP2_BASE + 0xE3)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/cec/include/
H A Dcec_hwreg.h129 #define REG_DVI_ATOP2_BASE 0x113400 macro
147 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
148 #define REG_DVI_ATOP2_70_H (REG_DVI_ATOP2_BASE + 0xE1)
149 #define REG_DVI_ATOP2_71_H (REG_DVI_ATOP2_BASE + 0xE3)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/cec/include/
H A Dcec_hwreg.h129 #define REG_DVI_ATOP2_BASE 0x113400UL macro
150 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
151 #define REG_DVI_ATOP2_70_H (REG_DVI_ATOP2_BASE + 0xE1)
152 #define REG_DVI_ATOP2_71_H (REG_DVI_ATOP2_BASE + 0xE3)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/cec/include/
H A Dcec_hwreg.h129 #define REG_DVI_ATOP2_BASE 0x113400UL macro
150 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
151 #define REG_DVI_ATOP2_70_H (REG_DVI_ATOP2_BASE + 0xE1)
152 #define REG_DVI_ATOP2_71_H (REG_DVI_ATOP2_BASE + 0xE3)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/cec/include/
H A Dcec_hwreg.h129 #define REG_DVI_ATOP2_BASE 0x113400UL macro
150 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
151 #define REG_DVI_ATOP2_70_H (REG_DVI_ATOP2_BASE + 0xE1)
152 #define REG_DVI_ATOP2_71_H (REG_DVI_ATOP2_BASE + 0xE3)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/cec/include/
H A Dcec_hwreg.h129 #define REG_DVI_ATOP2_BASE 0x113400UL macro
150 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
151 #define REG_DVI_ATOP2_70_H (REG_DVI_ATOP2_BASE + 0xE1)
152 #define REG_DVI_ATOP2_71_H (REG_DVI_ATOP2_BASE + 0xE3)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/cec/include/
H A Dcec_hwreg.h129 #define REG_DVI_ATOP2_BASE 0x113400UL macro
150 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
151 #define REG_DVI_ATOP2_70_H (REG_DVI_ATOP2_BASE + 0xE1)
152 #define REG_DVI_ATOP2_71_H (REG_DVI_ATOP2_BASE + 0xE3)
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h815 #define REG_DVI_ATOP2_00_L (REG_DVI_ATOP2_BASE + 0x00)
816 #define REG_DVI_ATOP2_00_H (REG_DVI_ATOP2_BASE + 0x01)
817 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
818 #define REG_DVI_ATOP2_06_H (REG_DVI_ATOP2_BASE + 0x0D)
819 #define REG_DVI_ATOP2_07_L (REG_DVI_ATOP2_BASE + 0x0E) // ENABLE_PATCH_HDCP_FOR_SEC_PC
820 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64)
821 #define REG_DVI_ATOP2_32_H (REG_DVI_ATOP2_BASE + 0x65)
822 #define REG_DVI_ATOP2_5E_L (REG_DVI_ATOP2_BASE + 0xBC)
823 #define REG_DVI_ATOP2_5E_H (REG_DVI_ATOP2_BASE + 0xBD)
824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h815 #define REG_DVI_ATOP2_00_L (REG_DVI_ATOP2_BASE + 0x00)
816 #define REG_DVI_ATOP2_00_H (REG_DVI_ATOP2_BASE + 0x01)
817 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
818 #define REG_DVI_ATOP2_06_H (REG_DVI_ATOP2_BASE + 0x0D)
819 #define REG_DVI_ATOP2_07_L (REG_DVI_ATOP2_BASE + 0x0E) // ENABLE_PATCH_HDCP_FOR_SEC_PC
820 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64)
821 #define REG_DVI_ATOP2_32_H (REG_DVI_ATOP2_BASE + 0x65)
822 #define REG_DVI_ATOP2_5E_L (REG_DVI_ATOP2_BASE + 0xBC)
823 #define REG_DVI_ATOP2_5E_H (REG_DVI_ATOP2_BASE + 0xBD)
824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h815 #define REG_DVI_ATOP2_00_L (REG_DVI_ATOP2_BASE + 0x00)
816 #define REG_DVI_ATOP2_00_H (REG_DVI_ATOP2_BASE + 0x01)
817 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
818 #define REG_DVI_ATOP2_06_H (REG_DVI_ATOP2_BASE + 0x0D)
819 #define REG_DVI_ATOP2_07_L (REG_DVI_ATOP2_BASE + 0x0E) // ENABLE_PATCH_HDCP_FOR_SEC_PC
820 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64)
821 #define REG_DVI_ATOP2_32_H (REG_DVI_ATOP2_BASE + 0x65)
822 #define REG_DVI_ATOP2_5E_L (REG_DVI_ATOP2_BASE + 0xBC)
823 #define REG_DVI_ATOP2_5E_H (REG_DVI_ATOP2_BASE + 0xBD)
824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h815 #define REG_DVI_ATOP2_00_L (REG_DVI_ATOP2_BASE + 0x00)
816 #define REG_DVI_ATOP2_00_H (REG_DVI_ATOP2_BASE + 0x01)
817 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
818 #define REG_DVI_ATOP2_06_H (REG_DVI_ATOP2_BASE + 0x0D)
819 #define REG_DVI_ATOP2_07_L (REG_DVI_ATOP2_BASE + 0x0E) // ENABLE_PATCH_HDCP_FOR_SEC_PC
820 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64)
821 #define REG_DVI_ATOP2_32_H (REG_DVI_ATOP2_BASE + 0x65)
822 #define REG_DVI_ATOP2_5E_L (REG_DVI_ATOP2_BASE + 0xBC)
823 #define REG_DVI_ATOP2_5E_H (REG_DVI_ATOP2_BASE + 0xBD)
824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h815 #define REG_DVI_ATOP2_00_L (REG_DVI_ATOP2_BASE + 0x00)
816 #define REG_DVI_ATOP2_00_H (REG_DVI_ATOP2_BASE + 0x01)
817 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
818 #define REG_DVI_ATOP2_06_H (REG_DVI_ATOP2_BASE + 0x0D)
819 #define REG_DVI_ATOP2_07_L (REG_DVI_ATOP2_BASE + 0x0E) // ENABLE_PATCH_HDCP_FOR_SEC_PC
820 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64)
821 #define REG_DVI_ATOP2_32_H (REG_DVI_ATOP2_BASE + 0x65)
822 #define REG_DVI_ATOP2_5E_L (REG_DVI_ATOP2_BASE + 0xBC)
823 #define REG_DVI_ATOP2_5E_H (REG_DVI_ATOP2_BASE + 0xBD)
824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h815 #define REG_DVI_ATOP2_00_L (REG_DVI_ATOP2_BASE + 0x00)
816 #define REG_DVI_ATOP2_00_H (REG_DVI_ATOP2_BASE + 0x01)
817 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
818 #define REG_DVI_ATOP2_06_H (REG_DVI_ATOP2_BASE + 0x0D)
819 #define REG_DVI_ATOP2_07_L (REG_DVI_ATOP2_BASE + 0x0E) // ENABLE_PATCH_HDCP_FOR_SEC_PC
820 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64)
821 #define REG_DVI_ATOP2_32_H (REG_DVI_ATOP2_BASE + 0x65)
822 #define REG_DVI_ATOP2_5E_L (REG_DVI_ATOP2_BASE + 0xBC)
823 #define REG_DVI_ATOP2_5E_H (REG_DVI_ATOP2_BASE + 0xBD)
824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h815 #define REG_DVI_ATOP2_00_L (REG_DVI_ATOP2_BASE + 0x00)
816 #define REG_DVI_ATOP2_00_H (REG_DVI_ATOP2_BASE + 0x01)
817 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
818 #define REG_DVI_ATOP2_06_H (REG_DVI_ATOP2_BASE + 0x0D)
819 #define REG_DVI_ATOP2_07_L (REG_DVI_ATOP2_BASE + 0x0E) // ENABLE_PATCH_HDCP_FOR_SEC_PC
820 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64)
821 #define REG_DVI_ATOP2_32_H (REG_DVI_ATOP2_BASE + 0x65)
822 #define REG_DVI_ATOP2_5E_L (REG_DVI_ATOP2_BASE + 0xBC)
823 #define REG_DVI_ATOP2_5E_H (REG_DVI_ATOP2_BASE + 0xBD)
824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h815 #define REG_DVI_ATOP2_00_L (REG_DVI_ATOP2_BASE + 0x00)
816 #define REG_DVI_ATOP2_00_H (REG_DVI_ATOP2_BASE + 0x01)
817 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C)
818 #define REG_DVI_ATOP2_06_H (REG_DVI_ATOP2_BASE + 0x0D)
819 #define REG_DVI_ATOP2_07_L (REG_DVI_ATOP2_BASE + 0x0E) // ENABLE_PATCH_HDCP_FOR_SEC_PC
820 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64)
821 #define REG_DVI_ATOP2_32_H (REG_DVI_ATOP2_BASE + 0x65)
822 #define REG_DVI_ATOP2_5E_L (REG_DVI_ATOP2_BASE + 0xBC)
823 #define REG_DVI_ATOP2_5E_H (REG_DVI_ATOP2_BASE + 0xBD)
824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0)
[all …]

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