| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 1370 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1371 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5308 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_forcemode()
5328 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 1400 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1401 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5408 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_forcemode()
5428 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 1435 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1436 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5450 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_forcemode()
5470 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 1400 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1401 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5408 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_forcemode()
5428 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 1442 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1443 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5423 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_forcemode()
5443 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 1435 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1436 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5450 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_forcemode()
5470 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 1373 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1374 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
6011 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_forcemode()
6031 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 1373 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1374 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
6014 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_forcemode()
6034 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 1535 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1536 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5721 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_forcemode()
5741 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 1373 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1374 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
6017 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_forcemode()
6037 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 1535 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1536 W2BYTEMSK(REG_COMBO_PHY1_P2_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5721 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_forcemode()
5741 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 2917 #define REG_COMBO_PHY1_P2_41_L (REG_COMBO_PHY1_P2_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 2919 #define REG_COMBO_PHY1_P2_41_L (REG_COMBO_PHY1_P2_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 2917 #define REG_COMBO_PHY1_P2_41_L (REG_COMBO_PHY1_P2_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 2919 #define REG_COMBO_PHY1_P2_41_L (REG_COMBO_PHY1_P2_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 2917 #define REG_COMBO_PHY1_P2_41_L (REG_COMBO_PHY1_P2_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 2919 #define REG_COMBO_PHY1_P2_41_L (REG_COMBO_PHY1_P2_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 2919 #define REG_COMBO_PHY1_P2_41_L (REG_COMBO_PHY1_P2_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 2917 #define REG_COMBO_PHY1_P2_41_L (REG_COMBO_PHY1_P2_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 2918 #define REG_COMBO_PHY1_P2_41_L (REG_COMBO_PHY1_P2_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 2917 #define REG_COMBO_PHY1_P2_41_L (REG_COMBO_PHY1_P2_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 2917 #define REG_COMBO_PHY1_P2_41_L (REG_COMBO_PHY1_P2_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 2917 #define REG_COMBO_PHY1_P2_41_L (REG_COMBO_PHY1_P2_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | hwreg_hdmi.h | 2917 #define REG_COMBO_PHY1_P2_41_L (REG_COMBO_PHY1_P2_BASE + 0x82) macro
|