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Searched refs:REG_COMBO_PHY1_P2_40_L (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c1366 if(R2BYTE(REG_COMBO_PHY1_P2_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5268 case INPUT_PORT_DVI2: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P2_40_L, irqbit); break; in Hal_DVI_irq_info()
5288 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c1396 if(R2BYTE(REG_COMBO_PHY1_P2_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5368 case INPUT_PORT_DVI2: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P2_40_L, irqbit); break; in Hal_DVI_irq_info()
5388 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c1431 if(R2BYTE(REG_COMBO_PHY1_P2_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5410 case INPUT_PORT_DVI2: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P2_40_L, irqbit); break; in Hal_DVI_irq_info()
5430 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c1396 if(R2BYTE(REG_COMBO_PHY1_P2_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5368 case INPUT_PORT_DVI2: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P2_40_L, irqbit); break; in Hal_DVI_irq_info()
5388 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c1438 if(R2BYTE(REG_COMBO_PHY1_P2_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5383 case INPUT_PORT_DVI2: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P2_40_L, irqbit); break; in Hal_DVI_irq_info()
5403 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c1431 if(R2BYTE(REG_COMBO_PHY1_P2_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5410 case INPUT_PORT_DVI2: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P2_40_L, irqbit); break; in Hal_DVI_irq_info()
5430 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c1369 if(R2BYTE(REG_COMBO_PHY1_P2_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5971 case INPUT_PORT_DVI2: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P2_40_L, irqbit); break; in Hal_DVI_irq_info()
5991 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c1369 if(R2BYTE(REG_COMBO_PHY1_P2_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5974 case INPUT_PORT_DVI2: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P2_40_L, irqbit); break; in Hal_DVI_irq_info()
5994 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c1531 if(R2BYTE(REG_COMBO_PHY1_P2_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5681 case INPUT_PORT_DVI2: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P2_40_L, irqbit); break; in Hal_DVI_irq_info()
5701 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c1369 if(R2BYTE(REG_COMBO_PHY1_P2_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5977 case INPUT_PORT_DVI2: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P2_40_L, irqbit); break; in Hal_DVI_irq_info()
5997 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c1531 if(R2BYTE(REG_COMBO_PHY1_P2_40_L) &BIT(7)) in _Hal_tmds_GetAutoEQDoneFlag()
5681 case INPUT_PORT_DVI2: u16reg_val = R2BYTEMSK(REG_COMBO_PHY1_P2_40_L, irqbit); break; in Hal_DVI_irq_info()
5701 case INPUT_PORT_DVI2: u16reg_add = REG_COMBO_PHY1_P2_40_L; break; in Hal_DVI_irq_mask()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h2915 #define REG_COMBO_PHY1_P2_40_L (REG_COMBO_PHY1_P2_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h2917 #define REG_COMBO_PHY1_P2_40_L (REG_COMBO_PHY1_P2_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h2915 #define REG_COMBO_PHY1_P2_40_L (REG_COMBO_PHY1_P2_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h2917 #define REG_COMBO_PHY1_P2_40_L (REG_COMBO_PHY1_P2_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h2915 #define REG_COMBO_PHY1_P2_40_L (REG_COMBO_PHY1_P2_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h2917 #define REG_COMBO_PHY1_P2_40_L (REG_COMBO_PHY1_P2_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h2917 #define REG_COMBO_PHY1_P2_40_L (REG_COMBO_PHY1_P2_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h2915 #define REG_COMBO_PHY1_P2_40_L (REG_COMBO_PHY1_P2_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h2916 #define REG_COMBO_PHY1_P2_40_L (REG_COMBO_PHY1_P2_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h2915 #define REG_COMBO_PHY1_P2_40_L (REG_COMBO_PHY1_P2_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h2915 #define REG_COMBO_PHY1_P2_40_L (REG_COMBO_PHY1_P2_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h2915 #define REG_COMBO_PHY1_P2_40_L (REG_COMBO_PHY1_P2_BASE + 0x80) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h2915 #define REG_COMBO_PHY1_P2_40_L (REG_COMBO_PHY1_P2_BASE + 0x80) macro