| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 1359 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1360 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5307 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_forcemode()
5327 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 1389 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1390 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5407 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_forcemode()
5427 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 1424 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1425 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5449 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_forcemode()
5469 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 1389 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1390 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5407 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_forcemode()
5427 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 1431 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1432 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5422 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_forcemode()
5442 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 1424 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1425 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5449 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_forcemode()
5469 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 1362 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1363 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
6010 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_forcemode()
6030 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 1362 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1363 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
6013 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_forcemode()
6033 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 1524 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1525 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5720 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_forcemode()
5740 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 1362 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1363 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
6016 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_forcemode()
6036 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 1524 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, BIT(15), BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
1525 W2BYTEMSK(REG_COMBO_PHY1_P1_41_L, 0, BIT(15)); in _Hal_tmds_GetAutoEQDoneFlag()
5720 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_forcemode()
5740 case INPUT_PORT_DVI1: u16reg_add = REG_COMBO_PHY1_P1_41_L; break; in Hal_DVI_irq_clear()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_hdmi.h | 2401 #define REG_COMBO_PHY1_P1_41_L (REG_COMBO_PHY1_P1_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_hdmi.h | 2403 #define REG_COMBO_PHY1_P1_41_L (REG_COMBO_PHY1_P1_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_hdmi.h | 2401 #define REG_COMBO_PHY1_P1_41_L (REG_COMBO_PHY1_P1_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_hdmi.h | 2403 #define REG_COMBO_PHY1_P1_41_L (REG_COMBO_PHY1_P1_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_hdmi.h | 2401 #define REG_COMBO_PHY1_P1_41_L (REG_COMBO_PHY1_P1_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_hdmi.h | 2403 #define REG_COMBO_PHY1_P1_41_L (REG_COMBO_PHY1_P1_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_hdmi.h | 2403 #define REG_COMBO_PHY1_P1_41_L (REG_COMBO_PHY1_P1_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_hdmi.h | 2401 #define REG_COMBO_PHY1_P1_41_L (REG_COMBO_PHY1_P1_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_hdmi.h | 2402 #define REG_COMBO_PHY1_P1_41_L (REG_COMBO_PHY1_P1_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_hdmi.h | 2401 #define REG_COMBO_PHY1_P1_41_L (REG_COMBO_PHY1_P1_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | hwreg_hdmi.h | 2401 #define REG_COMBO_PHY1_P1_41_L (REG_COMBO_PHY1_P1_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_hdmi.h | 2401 #define REG_COMBO_PHY1_P1_41_L (REG_COMBO_PHY1_P1_BASE + 0x82) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | hwreg_hdmi.h | 2401 #define REG_COMBO_PHY1_P1_41_L (REG_COMBO_PHY1_P1_BASE + 0x82) macro
|