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Searched refs:REG_COMBO_PHY0_P1_7E_L (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c3022 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3023 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3034 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3035 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3037 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3042 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3045 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3046 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3048 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3053 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c3059 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3060 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3071 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3072 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3074 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3079 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3082 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3083 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3085 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3090 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c3051 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3052 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3063 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3064 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3066 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3071 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3074 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3075 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3077 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3082 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c3059 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3060 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3071 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3072 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3074 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3079 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3082 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3083 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3085 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3090 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c3059 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3060 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3071 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3072 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3074 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3079 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3082 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3083 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3085 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3090 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c3051 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3052 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3063 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3064 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3066 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3071 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3074 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3075 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3077 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3082 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c3050 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3051 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3062 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3063 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3065 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3070 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3073 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3074 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3076 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3081 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c3053 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3054 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3065 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3066 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3068 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3073 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3076 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3077 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3079 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3084 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c3224 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3225 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3236 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3237 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3239 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3244 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3247 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3248 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3250 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3255 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c3053 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3054 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3065 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3066 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3068 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3073 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3076 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3077 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3079 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3084 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c3224 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(9)); in _Hal_tmds_EQCalibrationProc()
3225 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(9), BIT(9)); in _Hal_tmds_EQCalibrationProc()
3236 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3237 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane0, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3239 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3244 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
3247 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(6), BMASK(7:6)); in _Hal_tmds_EQCalibrationProc()
3248 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, ucEQCalCodeLane1, BMASK(4:0)); in _Hal_tmds_EQCalibrationProc()
3250 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, BIT(5), BIT(5)); in _Hal_tmds_EQCalibrationProc()
3255 W2BYTEMSK(REG_COMBO_PHY0_P1_7E_L, 0, BIT(5)); in _Hal_tmds_EQCalibrationProc()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h2265 #define REG_COMBO_PHY0_P1_7E_L (REG_COMBO_PHY0_P1_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h2267 #define REG_COMBO_PHY0_P1_7E_L (REG_COMBO_PHY0_P1_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h2265 #define REG_COMBO_PHY0_P1_7E_L (REG_COMBO_PHY0_P1_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h2267 #define REG_COMBO_PHY0_P1_7E_L (REG_COMBO_PHY0_P1_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h2265 #define REG_COMBO_PHY0_P1_7E_L (REG_COMBO_PHY0_P1_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h2267 #define REG_COMBO_PHY0_P1_7E_L (REG_COMBO_PHY0_P1_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h2267 #define REG_COMBO_PHY0_P1_7E_L (REG_COMBO_PHY0_P1_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h2265 #define REG_COMBO_PHY0_P1_7E_L (REG_COMBO_PHY0_P1_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h2266 #define REG_COMBO_PHY0_P1_7E_L (REG_COMBO_PHY0_P1_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h2265 #define REG_COMBO_PHY0_P1_7E_L (REG_COMBO_PHY0_P1_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h2265 #define REG_COMBO_PHY0_P1_7E_L (REG_COMBO_PHY0_P1_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h2265 #define REG_COMBO_PHY0_P1_7E_L (REG_COMBO_PHY0_P1_BASE + 0xFC) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h2265 #define REG_COMBO_PHY0_P1_7E_L (REG_COMBO_PHY0_P1_BASE + 0xFC) macro