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Searched refs:REG_COMBO_PHY0_P0_0B_L (Results 1 – 25 of 35) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_mux.c321 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
344 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
367 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
390 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
413 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c1889 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_mux.c324 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
358 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
392 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
426 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
459 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4006 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0xFFFF); // Clock enable in Hal_HDMI_init()
4074 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0x0001); // enable [0]: main link clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_mux.c321 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
345 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
369 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
393 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
417 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c2624 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_mux.c324 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
358 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
392 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
426 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
459 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4688 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0xFFFF); // Clock enable in Hal_HDMI_init()
4756 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0x0001); // enable [0]: main link clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_mux.c324 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
358 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
392 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
426 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
459 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4685 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0xFFFF); // Clock enable in Hal_HDMI_init()
4753 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0x0001); // enable [0]: main link clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_mux.c324 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
358 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
392 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
426 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
459 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4242 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0xFFFF); // Clock enable in Hal_HDMI_init()
4310 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0x0001); // enable [0]: main link clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_mux.c324 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
358 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
392 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
426 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
459 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4242 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0xFFFF); // Clock enable in Hal_HDMI_init()
4310 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0x0001); // enable [0]: main link clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_mux.c324 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
358 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
392 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
426 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
459 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4682 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0xFFFF); // Clock enable in Hal_HDMI_init()
4750 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0x0001); // enable [0]: main link clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_mux.c324 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0xFFFF); // Clock enable in Hal_SC_mux_set_dvi_mux()
358 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
392 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
426 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
459 W2BYTE(REG_COMBO_PHY0_P0_0B_L, 0x0001); // Clock enable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4051 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0xFFFF); // Clock enable in Hal_HDMI_init()
4119 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0x0001); // enable [0]: main link clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c4111 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0xFFFF); // Clock enable in Hal_HDMI_init()
4180 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0xFFFF); // Clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c4120 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0xFFFF); // Clock enable in Hal_HDMI_init()
4188 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0x0001); // enable [0]: main link clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c4111 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0xFFFF); // Clock enable in Hal_HDMI_init()
4180 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0xFFFF); // Clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c4120 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0xFFFF); // Clock enable in Hal_HDMI_init()
4188 W2BYTE(REG_COMBO_PHY0_P0_0B_L + u16bank_offset, 0x0001); // enable [0]: main link clock in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h1519 #define REG_COMBO_PHY0_P0_0B_L (REG_COMBO_PHY0_P0_BASE + 0x16) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h1521 #define REG_COMBO_PHY0_P0_0B_L (REG_COMBO_PHY0_P0_BASE + 0x16) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h1519 #define REG_COMBO_PHY0_P0_0B_L (REG_COMBO_PHY0_P0_BASE + 0x16) macro

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