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Searched refs:REG_COMBO_GP_TOP_29_L (Results 1 – 25 of 41) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_mux.c321 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
355 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
389 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
423 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0x00, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
456 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c3992 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0x00, 0xFF); // P3 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_mux.c321 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
355 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
389 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
423 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0x00, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
456 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_mux.c321 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
355 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
389 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
423 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0x00, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
456 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4671 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0x00, 0xFF); // P3 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_mux.c321 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
355 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
389 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
423 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0x00, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
456 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_mux.c321 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
355 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
389 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
423 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0x00, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
456 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_mux.c321 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
355 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
389 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
423 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0x00, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
456 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4668 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0x00, 0xFF); // P3 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_mux.c321 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
355 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
389 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
423 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0x00, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
456 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0xFF, 0xFF); // P3 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4037 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0x00, 0xFF); // P3 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdcp/
H A DregHDCP.h419 #define REG_COMBO_GP_TOP_29_L 0x29U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/hdcp/
H A DregHDCP.h419 #define REG_COMBO_GP_TOP_29_L 0x29U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdcp/
H A DregHDCP.h419 #define REG_COMBO_GP_TOP_29_L 0x29U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/hdcp/
H A DregHDCP.h419 #define REG_COMBO_GP_TOP_29_L 0x29U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdcp/
H A DregHDCP.h419 #define REG_COMBO_GP_TOP_29_L 0x29U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/hdcp/
H A DregHDCP.h419 #define REG_COMBO_GP_TOP_29_L 0x29U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/hdcp/
H A DregHDCP.h419 #define REG_COMBO_GP_TOP_29_L 0x29U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdcp/
H A DregHDCP.h419 #define REG_COMBO_GP_TOP_29_L 0x29U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/hdcp/
H A DregHDCP.h419 #define REG_COMBO_GP_TOP_29_L 0x29U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdcp/
H A DregHDCP.h419 #define REG_COMBO_GP_TOP_29_L 0x29U macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c4097 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0x00, 0xFF); // P3 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c4106 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0x00, 0xFF); // P3 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c4097 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0x00, 0xFF); // P3 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c4106 MDrv_WriteByteMask(REG_COMBO_GP_TOP_29_L, 0x00, 0xFF); // P3 dec_hdcp clock enable in Hal_HDMI_init()

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