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Searched refs:REG_COMBO_GP_TOP_21_L (Results 1 – 25 of 41) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_mux.c320 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
354 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
388 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0x00, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
422 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
455 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c3991 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0x00, 0xFF); // P2 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_mux.c320 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
354 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
388 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0x00, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
422 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
455 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_mux.c320 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
354 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
388 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0x00, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
422 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
455 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4670 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0x00, 0xFF); // P2 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_mux.c320 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
354 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
388 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0x00, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
422 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
455 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_mux.c320 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
354 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
388 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0x00, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
422 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
455 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_mux.c320 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
354 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
388 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0x00, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
422 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
455 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4667 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0x00, 0xFF); // P2 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_mux.c320 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
354 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
388 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0x00, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
422 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
455 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0xFF, 0xFF); // P2 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4036 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0x00, 0xFF); // P2 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdcp/
H A DregHDCP.h411 #define REG_COMBO_GP_TOP_21_L 0x21U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/hdcp/
H A DregHDCP.h411 #define REG_COMBO_GP_TOP_21_L 0x21U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdcp/
H A DregHDCP.h411 #define REG_COMBO_GP_TOP_21_L 0x21U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/hdcp/
H A DregHDCP.h411 #define REG_COMBO_GP_TOP_21_L 0x21U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdcp/
H A DregHDCP.h411 #define REG_COMBO_GP_TOP_21_L 0x21U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/hdcp/
H A DregHDCP.h411 #define REG_COMBO_GP_TOP_21_L 0x21U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/hdcp/
H A DregHDCP.h411 #define REG_COMBO_GP_TOP_21_L 0x21U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdcp/
H A DregHDCP.h411 #define REG_COMBO_GP_TOP_21_L 0x21U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/hdcp/
H A DregHDCP.h411 #define REG_COMBO_GP_TOP_21_L 0x21U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdcp/
H A DregHDCP.h411 #define REG_COMBO_GP_TOP_21_L 0x21U macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c4096 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0x00, 0xFF); // P2 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c4105 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0x00, 0xFF); // P2 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c4096 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0x00, 0xFF); // P2 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c4105 MDrv_WriteByteMask(REG_COMBO_GP_TOP_21_L, 0x00, 0xFF); // P2 dec_hdcp clock enable in Hal_HDMI_init()

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