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Searched refs:REG_COMBO_GP_TOP_19_L (Results 1 – 25 of 41) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_mux.c319 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
353 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0x00, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
387 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
421 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
454 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c3990 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0x00, 0xFF); // P1 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_mux.c319 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
353 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0x00, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
387 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
421 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
454 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_mux.c319 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
353 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0x00, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
387 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
421 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
454 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4669 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0x00, 0xFF); // P1 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_mux.c319 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
353 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0x00, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
387 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
421 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
454 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_mux.c319 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
353 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0x00, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
387 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
421 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
454 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_mux.c319 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
353 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0x00, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
387 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
421 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
454 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4666 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0x00, 0xFF); // P1 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_mux.c319 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock disable in Hal_SC_mux_set_dvi_mux()
353 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0x00, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
387 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
421 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
454 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0xFF, 0xFF); // P1 dec_hdcp clock enable in Hal_SC_mux_set_dvi_mux()
H A Dmhal_hdmi.c4035 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0x00, 0xFF); // P1 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdcp/
H A DregHDCP.h403 #define REG_COMBO_GP_TOP_19_L 0x19U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/hdcp/
H A DregHDCP.h403 #define REG_COMBO_GP_TOP_19_L 0x19U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdcp/
H A DregHDCP.h403 #define REG_COMBO_GP_TOP_19_L 0x19U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/hdcp/
H A DregHDCP.h403 #define REG_COMBO_GP_TOP_19_L 0x19U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdcp/
H A DregHDCP.h403 #define REG_COMBO_GP_TOP_19_L 0x19U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/hdcp/
H A DregHDCP.h403 #define REG_COMBO_GP_TOP_19_L 0x19U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/hdcp/
H A DregHDCP.h403 #define REG_COMBO_GP_TOP_19_L 0x19U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdcp/
H A DregHDCP.h403 #define REG_COMBO_GP_TOP_19_L 0x19U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/hdcp/
H A DregHDCP.h403 #define REG_COMBO_GP_TOP_19_L 0x19U macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdcp/
H A DregHDCP.h403 #define REG_COMBO_GP_TOP_19_L 0x19U macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c4095 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0x00, 0xFF); // P1 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c4104 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0x00, 0xFF); // P1 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c4095 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0x00, 0xFF); // P1 dec_hdcp clock enable in Hal_HDMI_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c4104 MDrv_WriteByteMask(REG_COMBO_GP_TOP_19_L, 0x00, 0xFF); // P1 dec_hdcp clock enable in Hal_HDMI_init()

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