| /utopia/UTPA2-700.0.x/modules/pws/hal/maldives/pws/ |
| H A D | regCLKGEN.h | 280 #define REG_CKG_FICLK_F2 0x1E30 macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/k6/pws/ |
| H A D | regCLKGEN.h | 280 #define REG_CKG_FICLK_F2 0x1E30 macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/macan/pws/ |
| H A D | regCLKGEN.h | 280 #define REG_CKG_FICLK_F2 0x1E30UL macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/mooney/pws/ |
| H A D | regCLKGEN.h | 280 #define REG_CKG_FICLK_F2 0x1E30UL macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/messi/pws/ |
| H A D | regCLKGEN.h | 280 #define REG_CKG_FICLK_F2 0x1E30UL macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/manhattan/pws/ |
| H A D | regCLKGEN.h | 280 #define REG_CKG_FICLK_F2 0x1E30UL macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/k6lite/pws/ |
| H A D | regCLKGEN.h | 280 #define REG_CKG_FICLK_F2 0x1E30 macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/M7821/pws/ |
| H A D | regCLKGEN.h | 280 #define REG_CKG_FICLK_F2 0x1E30UL macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/mainz/pws/ |
| H A D | regCLKGEN.h | 280 #define REG_CKG_FICLK_F2 0x1E30UL macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/mustang/pws/ |
| H A D | regCLKGEN.h | 280 #define REG_CKG_FICLK_F2 0x1E30 macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/maxim/pws/ |
| H A D | regCLKGEN.h | 280 #define REG_CKG_FICLK_F2 0x1E30UL macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/M7621/pws/ |
| H A D | regCLKGEN.h | 280 #define REG_CKG_FICLK_F2 0x1E30UL macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/curry/pws/ |
| H A D | regCLKGEN.h | 280 #define REG_CKG_FICLK_F2 0x1E30 macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/kano/pws/ |
| H A D | regCLKGEN.h | 280 #define REG_CKG_FICLK_F2 0x1E30 macro
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| /utopia/UTPA2-700.0.x/modules/pws/hal/maserati/pws/ |
| H A D | regCLKGEN.h | 280 #define REG_CKG_FICLK_F2 0x1E30UL macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | mhal_xc_chip_config.h | 494 #define REG_CKG_FICLK_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | mhal_xc_chip_config.h | 494 #define REG_CKG_FICLK_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/drv/xc/ |
| H A D | mvideo.c | 494 … MDrv_WriteRegBit(REG_CKG_FICLK_F2, ENABLE, CKG_FICLK_F2_GATED); // Enable clock in MApi_XC_Exit_U2()
542 … MDrv_WriteRegBit(REG_CKG_FICLK_F2, ENABLE, CKG_FICLK_F2_GATED); // Enable clock in MApi_XC_Exit_U2()
582 … MDrv_WriteRegBit(REG_CKG_FICLK_F2, ENABLE, CKG_FICLK_F2_GATED); // Enable clock in MApi_XC_Exit_U2()
1132 …MDrv_WriteByteMask(REG_CKG_FICLK_F2, CKG_FICLK_F2_FLK, CKG_FICLK_F2_MASK); // select FClk… in _MApi_XC_Init_WithoutCreateMutex()
1133 … MDrv_WriteRegBit(REG_CKG_FICLK_F2, DISABLE, CKG_FICLK_F2_INVERT); // Not Invert in _MApi_XC_Init_WithoutCreateMutex()
1134 …MDrv_WriteRegBit(REG_CKG_FICLK_F2, DISABLE, CKG_FICLK_F2_GATED); // Enable clock in _MApi_XC_Init_WithoutCreateMutex()
1176 …MDrv_WriteByteMask(REG_CKG_FICLK_F2, CKG_FICLK_F2_FLK, CKG_FICLK_F2_MASK); // select FClk… in _MApi_XC_Init_WithoutCreateMutex()
1177 … MDrv_WriteRegBit(REG_CKG_FICLK_F2, DISABLE, CKG_FICLK_F2_INVERT); // Not Invert in _MApi_XC_Init_WithoutCreateMutex()
1178 …MDrv_WriteRegBit(REG_CKG_FICLK_F2, DISABLE, CKG_FICLK_F2_GATED); // Enable clock in _MApi_XC_Init_WithoutCreateMutex()
1210 …MDrv_WriteByteMask(REG_CKG_FICLK_F2, CKG_FICLK_F2_FLK, CKG_FICLK_F2_MASK); // select FClk… in _MApi_XC_Init_WithoutCreateMutex()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | mhal_xc_chip_config.h | 649 #define REG_CKG_FICLK_F2 (REG_CLKGEN0_BASE + 0xA3 ) // for Monaco, this CLK is for VE using,… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | mhal_xc_chip_config.h | 647 #define REG_CKG_FICLK_F2 (REG_CLKGEN0_BASE + 0xA3 ) // for Monaco, this CLK is for VE using,… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | mhal_xc_chip_config.h | 661 #define REG_CKG_FICLK_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | mhal_xc_chip_config.h | 667 #define REG_CKG_FICLK_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | mhal_xc_chip_config.h | 667 #define REG_CKG_FICLK_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | mhal_xc_chip_config.h | 669 #define REG_CKG_FICLK_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p… macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | mhal_xc_chip_config.h | 644 #define REG_CKG_FICLK_F2 (REG_CLKGEN0_BASE + 0xA3 ) // for Monaco, this CLK is for VE using,… macro
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