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Searched refs:REG_ADC_DTOPB_FE_L (Results 1 – 25 of 33) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_adctbl.c130 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*All*/, },
1532 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x05/*RGB*/,
1603 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1612 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1621 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1690 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1699 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1708 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1717 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1726 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x0A/*SW_UG*/,
[all …]
H A Dhwreg_adc_dtopb.h362 #define REG_ADC_DTOPB_FE_L (REG_ADC_DTOPB_BASE + 0xFF) // for delay loop macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_adctbl.c130 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*All*/, },
1532 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x05/*RGB*/,
1603 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1612 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1621 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1690 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1699 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1708 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1717 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1726 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x0A/*SW_UG*/,
[all …]
H A Dhwreg_adc_dtopb.h362 #define REG_ADC_DTOPB_FE_L (REG_ADC_DTOPB_BASE + 0xFF) // for delay loop macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_adctbl.c130 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*All*/, },
1532 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x05/*RGB*/,
1603 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1612 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1621 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1690 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1699 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1708 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1717 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1726 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x0A/*SW_UG*/,
[all …]
H A Dhwreg_adc_dtopb.h362 #define REG_ADC_DTOPB_FE_L (REG_ADC_DTOPB_BASE + 0xFF) // for delay loop macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_adctbl.c130 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*All*/, },
1580 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x05/*RGB*/,
1652 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1661 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1670 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1739 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1748 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1757 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1766 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1775 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x0A/*SW_UG*/,
[all …]
H A Dhwreg_adc_dtopb.h362 #define REG_ADC_DTOPB_FE_L (REG_ADC_DTOPB_BASE + 0xFF) // for delay loop macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_adctbl.c130 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*All*/, },
1532 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x05/*RGB*/,
1603 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1612 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1621 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1690 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1699 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1708 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1717 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1726 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x0A/*SW_UG*/,
[all …]
H A Dhwreg_adc_dtopb.h362 #define REG_ADC_DTOPB_FE_L (REG_ADC_DTOPB_BASE + 0xFF) // for delay loop macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_adctbl.c130 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*All*/, },
1532 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x05/*RGB*/,
1603 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1612 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1621 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1690 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1699 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1708 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1717 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1726 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x0A/*SW_UG*/,
[all …]
H A Dhwreg_adc_dtopb.h362 #define REG_ADC_DTOPB_FE_L (REG_ADC_DTOPB_BASE + 0xFF) // for delay loop macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_adctbl.c130 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*All*/, },
1580 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x05/*RGB*/,
1652 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1661 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1670 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1739 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1748 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1757 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1766 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1775 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x0A/*SW_UG*/,
[all …]
H A Dhwreg_adc_dtopb.h362 #define REG_ADC_DTOPB_FE_L (REG_ADC_DTOPB_BASE + 0xFF) // for delay loop macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_adctbl.c1515 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x05/*RGB*/,
1587 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1596 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1605 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1674 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1683 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1692 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1701 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1710 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x0A/*SW_UG*/,
1730 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*ALL*/, },
[all …]
H A Dhwreg_adc_dtopb.h362 #define REG_ADC_DTOPB_FE_L (REG_ADC_DTOPB_BASE + 0xFF) // for delay loop macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_adctbl.c1515 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x05/*RGB*/,
1587 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1596 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1605 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1674 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1683 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1692 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1701 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1710 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x0A/*SW_UG*/,
1730 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*ALL*/, },
[all …]
H A Dhwreg_adc_dtopb.h362 #define REG_ADC_DTOPB_FE_L (REG_ADC_DTOPB_BASE + 0xFF) // for delay loop macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_adctbl.c1515 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x05/*RGB*/,
1587 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1596 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1605 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1674 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1683 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1692 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1701 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1710 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x0A/*SW_UG*/,
1730 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*ALL*/, },
[all …]
H A Dhwreg_adc_dtopb.h362 #define REG_ADC_DTOPB_FE_L (REG_ADC_DTOPB_BASE + 0xFF) // for delay loop macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_adctbl.c1467 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x05/*RGB*/,
1538 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1547 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1556 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1625 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1634 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1643 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1652 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*SW_UG*/,
1661 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x0A/*SW_UG*/,
1681 { DRV_ADC_REG(REG_ADC_DTOPB_FE_L), 0xFF, 0x00, 0x01/*ALL*/, },
[all …]
H A Dhwreg_adc_dtopb.h362 #define REG_ADC_DTOPB_FE_L (REG_ADC_DTOPB_BASE + 0xFF) // for delay loop macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_adc.c582 if(u32Addr == REG_ADC_DTOPB_FE_L) in Hal_ADC_LoadTable()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_adc.c582 if(u32Addr == REG_ADC_DTOPB_FE_L) in Hal_ADC_LoadTable()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_adc.c505 if(u32Addr == REG_ADC_DTOPB_FE_L) in Hal_ADC_LoadTable()

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