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Searched refs:REG_ADC_ATOP_5A_L (Results 1 – 25 of 46) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_adctbl.c1642 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*SW_UG*/,
1645 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x10/*SW_UG*/,
1747 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1748 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x08, 0x00, 0x00/*ALL*/, },
1791 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x00/*ALL*/, },
1792 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x40, 0x00, 0x00/*ALL*/, },
1834 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1835 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x00/*ALL*/, },
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_adctbl.c1642 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*SW_UG*/,
1645 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x10/*SW_UG*/,
1747 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1748 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x08, 0x00, 0x00/*ALL*/, },
1791 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x00/*ALL*/, },
1792 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x40, 0x00, 0x00/*ALL*/, },
1834 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1835 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x00/*ALL*/, },
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_adctbl.c1642 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*SW_UG*/,
1645 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x10/*SW_UG*/,
1747 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1748 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x08, 0x00, 0x00/*ALL*/, },
1791 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x00/*ALL*/, },
1792 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x40, 0x00, 0x00/*ALL*/, },
1834 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1835 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x00/*ALL*/, },
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_adctbl.c1691 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*SW_UG*/,
1694 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x10/*SW_UG*/,
1796 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1797 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x08, 0x00, 0x00/*ALL*/, },
1840 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x00/*ALL*/, },
1841 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x40, 0x00, 0x00/*ALL*/, },
1883 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1884 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x00/*ALL*/, },
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_adctbl.c1642 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*SW_UG*/,
1645 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x10/*SW_UG*/,
1747 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1748 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x08, 0x00, 0x00/*ALL*/, },
1791 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x00/*ALL*/, },
1792 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x40, 0x00, 0x00/*ALL*/, },
1834 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1835 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x00/*ALL*/, },
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_adctbl.c1642 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*SW_UG*/,
1645 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x10/*SW_UG*/,
1747 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1748 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x08, 0x00, 0x00/*ALL*/, },
1791 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x00/*ALL*/, },
1792 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x40, 0x00, 0x00/*ALL*/, },
1834 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1835 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x00/*ALL*/, },
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_adctbl.c1691 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*SW_UG*/,
1694 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x10/*SW_UG*/,
1796 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1797 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x08, 0x00, 0x00/*ALL*/, },
1840 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x00/*ALL*/, },
1841 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x40, 0x00, 0x00/*ALL*/, },
1883 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1884 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x00/*ALL*/, },
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_adctbl.c1626 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*SW_UG*/,
1629 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x10/*SW_UG*/,
1731 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1732 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x08, 0x00, 0x00/*ALL*/, },
1780 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1781 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x00/*ALL*/, },
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_adctbl.c1626 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*SW_UG*/,
1629 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x10/*SW_UG*/,
1731 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1732 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x08, 0x00, 0x00/*ALL*/, },
1780 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1781 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x00/*ALL*/, },
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_adctbl.c1626 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*SW_UG*/,
1629 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x10/*SW_UG*/,
1731 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1732 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x08, 0x00, 0x00/*ALL*/, },
1780 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1781 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x00/*ALL*/, },
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_adctbl.c1577 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*SW_UG*/,
1580 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x10/*SW_UG*/,
1682 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1683 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x08, 0x00, 0x00/*ALL*/, },
1731 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x01, 0x00, 0x01/*ALL*/, },
1732 { DRV_ADC_REG(REG_ADC_ATOP_5A_L), 0x10, 0x00, 0x00/*ALL*/, },
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_offline.c255 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
274 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
301 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_offline.c261 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
280 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
307 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_offline.c255 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
274 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
301 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_offline.c261 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
280 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
307 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_offline.c261 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
280 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
307 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_offline.c261 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
280 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
307 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_offline.c261 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
280 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
307 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_offline.c261 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
280 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
307 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_offline.c261 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_AV()
279 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0xC0);//PD_LDO25_ADCA,PD_LDO25_ADCB in Hal_XC_SetOffLineToSog_YUV()
304 MDrv_Write2ByteMask(REG_ADC_ATOP_5A_L, 0, 0x40);//PD_LDO25_ADCA in Hal_XC_SetOffLineToHv()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_adc.c1180 W2BYTEMSK(REG_ADC_ATOP_5A_L, 0x00 , BIT(0) ); in Hal_ADC_dtop_internaldc_setting()
1195 W2BYTEMSK(REG_ADC_ATOP_5A_L, BIT(0) , BIT(0) ); in Hal_ADC_dtop_internaldc_setting()
1473 W2BYTEMSK(REG_ADC_ATOP_5A_L, 0, BIT(5)|BIT(6)|BIT(7)); in Hal_ADC_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_adc.c1180 W2BYTEMSK(REG_ADC_ATOP_5A_L, 0x00 , BIT(0) ); in Hal_ADC_dtop_internaldc_setting()
1195 W2BYTEMSK(REG_ADC_ATOP_5A_L, BIT(0) , BIT(0) ); in Hal_ADC_dtop_internaldc_setting()
1473 W2BYTEMSK(REG_ADC_ATOP_5A_L, 0, BIT(5)|BIT(6)|BIT(7)); in Hal_ADC_init()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_adc_atop.h285 #define REG_ADC_ATOP_5A_L (REG_ADC_ATOP_BASE + 0xB4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_adc_atop.h285 #define REG_ADC_ATOP_5A_L (REG_ADC_ATOP_BASE + 0xB4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_adc_atop.h285 #define REG_ADC_ATOP_5A_L (REG_ADC_ATOP_BASE + 0xB4) macro

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