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Searched refs:REG_ADC_ATOPB_53_H (Results 1 – 14 of 14) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_adctbl.c1781 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1789 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1797 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1798 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x20, 0x00, 0x00/*ALL*/, },
1809 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_atop.h529 #define REG_ADC_ATOPB_53_H (REG_ADC_ATOPB_BASE + 0xA7) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_adctbl.c1781 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1789 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1797 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1798 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x20, 0x00, 0x00/*ALL*/, },
1809 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_atop.h529 #define REG_ADC_ATOPB_53_H (REG_ADC_ATOPB_BASE + 0xA7) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_adctbl.c1781 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1789 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1797 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1798 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x20, 0x00, 0x00/*ALL*/, },
1809 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_atop.h529 #define REG_ADC_ATOPB_53_H (REG_ADC_ATOPB_BASE + 0xA7) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_adctbl.c1830 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1838 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1846 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1847 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x20, 0x00, 0x00/*ALL*/, },
1858 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_atop.h529 #define REG_ADC_ATOPB_53_H (REG_ADC_ATOPB_BASE + 0xA7) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_adctbl.c1781 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1789 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1797 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1798 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x20, 0x00, 0x00/*ALL*/, },
1809 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_atop.h529 #define REG_ADC_ATOPB_53_H (REG_ADC_ATOPB_BASE + 0xA7) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_adctbl.c1781 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1789 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1797 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1798 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x20, 0x00, 0x00/*ALL*/, },
1809 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_atop.h529 #define REG_ADC_ATOPB_53_H (REG_ADC_ATOPB_BASE + 0xA7) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_adctbl.c1830 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x18, 0x00, 0x08/*ALL*/, },
1838 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
1846 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x18, 0x00, 0x10/*ALL*/, },
1847 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x20, 0x00, 0x00/*ALL*/, },
1858 { DRV_ADC_REG(REG_ADC_ATOPB_53_H), 0x01, 0x00, 0x01/*ALL*/, },
H A Dhwreg_adc_atop.h529 #define REG_ADC_ATOPB_53_H (REG_ADC_ATOPB_BASE + 0xA7) macro