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Searched refs:MIU_FRC_G5REQUEST_MASK (Results 1 – 11 of 11) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_frc.c555 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG5Mask |= MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Enable_MiuMask()
563 pXCResourcePrivate->sthal_FRC.FRC_Miu1Mask.u16MiuG5Mask |= MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Enable_MiuMask()
583 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG5Mask &= ~MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Disable_MiuMask()
585 pXCResourcePrivate->sthal_FRC.FRC_Miu1Mask.u16MiuG5Mask &= ~MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Disable_MiuMask()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_frc.c733 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG5Mask |= MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Enable_MiuMask()
741 pXCResourcePrivate->sthal_FRC.FRC_Miu1Mask.u16MiuG5Mask |= MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Enable_MiuMask()
761 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG5Mask &= ~MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Disable_MiuMask()
763 pXCResourcePrivate->sthal_FRC.FRC_Miu1Mask.u16MiuG5Mask &= ~MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Disable_MiuMask()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_frc.c716 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG5Mask |= MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Enable_MiuMask()
724 pXCResourcePrivate->sthal_FRC.FRC_Miu1Mask.u16MiuG5Mask |= MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Enable_MiuMask()
744 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG5Mask &= ~MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Disable_MiuMask()
746 pXCResourcePrivate->sthal_FRC.FRC_Miu1Mask.u16MiuG5Mask &= ~MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Disable_MiuMask()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_frc.c694 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG5Mask |= MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Enable_MiuMask()
702 pXCResourcePrivate->sthal_FRC.FRC_Miu1Mask.u16MiuG5Mask |= MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Enable_MiuMask()
722 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG5Mask &= ~MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Disable_MiuMask()
724 pXCResourcePrivate->sthal_FRC.FRC_Miu1Mask.u16MiuG5Mask &= ~MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Disable_MiuMask()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_frc.c694 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG5Mask |= MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Enable_MiuMask()
702 pXCResourcePrivate->sthal_FRC.FRC_Miu1Mask.u16MiuG5Mask |= MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Enable_MiuMask()
722 pXCResourcePrivate->sthal_FRC.FRC_Miu0Mask.u16MiuG5Mask &= ~MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Disable_MiuMask()
724 pXCResourcePrivate->sthal_FRC.FRC_Miu1Mask.u16MiuG5Mask &= ~MIU_FRC_G5REQUEST_MASK; in MHal_FRC_Disable_MiuMask()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h1121 #define MIU_FRC_G5REQUEST_MASK (0x7FFF) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h1084 #define MIU_FRC_G5REQUEST_MASK (0x7FFF) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h1141 #define MIU_FRC_G5REQUEST_MASK (0x7FFF) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h1078 #define MIU_FRC_G5REQUEST_MASK (0x7FFF) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h1146 #define MIU_FRC_G5REQUEST_MASK (0x7FFF) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h1125 #define MIU_FRC_G5REQUEST_MASK (0x7FFF) macro