Home
last modified time | relevance | path

Searched refs:MDrv_MFC_WriteBit (Results 1 – 25 of 48) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/mfc/hal/maserati/mfc/
H A Dmdrv_mfc_scalerop.c288 MDrv_MFC_WriteBit(0x2A2C, 1, _BIT0); in MDrv_MFC_SetVCO()
303 MDrv_MFC_WriteBit(0x2A1B, _ENABLE, _BIT3); in MDrv_MFC_SetLvdsSSC()
322 MDrv_MFC_WriteBit(0x2A1B, _DISABLE, _BIT3); in MDrv_MFC_SetLvdsSSC()
482 MDrv_MFC_WriteBit(0x2A2C, 1, _BIT0); in msLPLL_SetVCO()
499 MDrv_MFC_WriteBit(0x2080, _DISABLE, _BIT0); // disable film32 in msSetOutDClk()
503 MDrv_MFC_WriteBit(0x2080, _ENABLE, _BIT0); // enable film32 in msSetOutDClk()
506 MDrv_MFC_WriteBit(0x2A18, 0, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
570 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
618 MDrv_MFC_WriteBit(0x30A0, 1, _BIT1);
765 MDrv_MFC_WriteBit(0x2080, _DISABLE, _BIT0); // disable film32 in MDrv_MFC_SetOutDClk()
[all …]
H A Dmdrv_mfc_scalerip.c128 MDrv_MFC_WriteBit(0x2005, 1, _BIT5); in MDrv_MFC_IP_SetMemMode()
147 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); in MDrv_MFC_InitializeRx()
152 MDrv_MFC_WriteBit(0x2214, 1, _BIT2); //LVDS in MDrv_MFC_InitializeRx()
156 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); //TTL in MDrv_MFC_InitializeRx()
159 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); //TTL in MDrv_MFC_InitializeRx()
161 MDrv_MFC_WriteBit(0x2214, 1, _BIT3); in MDrv_MFC_InitializeRx()
162 MDrv_MFC_WriteBit(0x2214, 1, _BIT5); in MDrv_MFC_InitializeRx()
164 MDrv_MFC_WriteBit(0x2216, 1, _BIT3); in MDrv_MFC_InitializeRx()
165 MDrv_MFC_WriteBit(0x2216, 1, _BIT4); in MDrv_MFC_InitializeRx()
167 MDrv_MFC_WriteBit(0x221E, 1, _BIT3); in MDrv_MFC_InitializeRx()
[all …]
H A Dmdrv_mfc_mcu.c108 MDrv_MFC_WriteBit(0x3C66, 1, _BIT1); // XD_MCU1[0xC0] = 0; in MDrv_MFC_McuWatchDogClear()
130 MDrv_MFC_WriteBit(0x1018, 1, _BIT3); in MDrv_MFC_McuICacheCtrl()
131 MDrv_MFC_WriteBit(0x2BA0, 0, _BIT0); in MDrv_MFC_McuICacheCtrl()
135 MDrv_MFC_WriteBit(0x1018, 0, _BIT3); in MDrv_MFC_McuICacheCtrl()
136 MDrv_MFC_WriteBit(0x2BA0, 1, _BIT0); in MDrv_MFC_McuICacheCtrl()
171 MDrv_MFC_WriteBit(0x1E06, bEnable, _BIT5); // [0] in MDrv_MFC_McuUsePLL()
202 MDrv_MFC_WriteBit(0x2401, 0, _BIT0); // Vsync change irq in MDrv_MFC_SetInterrupt()
203 MDrv_MFC_WriteBit(0x2406, 0, _BIT1); // OP Vsync irq in MDrv_MFC_SetInterrupt()
204 MDrv_MFC_WriteBit(0x2406, 0, _BIT3); // end of DE irq in MDrv_MFC_SetInterrupt()
212 MDrv_MFC_WriteBit(0x2401, 1, _BIT0); // Vsync change irq in MDrv_MFC_SetInterrupt()
[all …]
H A Dmdrv_mfc_panel.c566 MDrv_MFC_WriteBit(0x20C0, gmfcSysInfo.u8PanelCSC, _BIT0); // [0]:CSC [1]:dither [2]:round in msInitializeColorMatrix()
587 MDrv_MFC_WriteBit(0x23F0, 1, _BIT3);//reg_ctrl_low_sel-----I-Chang 0909 in msInitializeTcon()
588 MDrv_MFC_WriteBit(0x23F0, 1, _BIT2);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
589 MDrv_MFC_WriteBit(0x23F0, 0, _BIT1);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
590 MDrv_MFC_WriteBit(0x23F0, 0, _BIT0);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
591 MDrv_MFC_WriteBit(0x2313, 1, _BIT7);//reg_tp_md_sel-----I-Chang 0909 in msInitializeTcon()
592 MDrv_MFC_WriteBit(0x230F, 1, _BIT3);//Request by Bryan, control load-----I-Chang 0901 in msInitializeTcon()
595 MDrv_MFC_WriteBit(0x238C, 0, _BIT0); //Output Enable FLK //j081031 in msInitializeTcon()
606 MDrv_MFC_WriteBit(0x2052, 0, _BIT0);//Only for visit; PC mode on-----I-Chang 0829 in msInitializeTcon()
608 MDrv_MFC_WriteBit(0x2300, gmfcSysInfo.u8PanelBlankCPVC, _BIT6); in msInitializeTcon()
[all …]
H A Dmdrv_mfc_fb.c580 MDrv_MFC_WriteBit(0x1329, _ENABLE, _BIT7); in MDrv_MFC_SetMiuSSC()
586 MDrv_MFC_WriteBit(0x1329, _DISABLE, _BIT7); in MDrv_MFC_SetMiuSSC()
592 MDrv_MFC_WriteBit(0x1221, 0, _BIT7); in MDrv_MFC_MIUPLL_Reset()
593 MDrv_MFC_WriteBit(0x1221, 0, _BIT6); in MDrv_MFC_MIUPLL_Reset()
594 MDrv_MFC_WriteBit(0x1221, 0, _BIT5); in MDrv_MFC_MIUPLL_Reset()
/utopia/UTPA2-700.0.x/modules/mfc/hal/macan/mfc/
H A Dmdrv_mfc_scalerop.c288 MDrv_MFC_WriteBit(0x2A2C, 1, _BIT0); in MDrv_MFC_SetVCO()
303 MDrv_MFC_WriteBit(0x2A1B, _ENABLE, _BIT3); in MDrv_MFC_SetLvdsSSC()
322 MDrv_MFC_WriteBit(0x2A1B, _DISABLE, _BIT3); in MDrv_MFC_SetLvdsSSC()
482 MDrv_MFC_WriteBit(0x2A2C, 1, _BIT0); in msLPLL_SetVCO()
499 MDrv_MFC_WriteBit(0x2080, _DISABLE, _BIT0); // disable film32 in msSetOutDClk()
503 MDrv_MFC_WriteBit(0x2080, _ENABLE, _BIT0); // enable film32 in msSetOutDClk()
506 MDrv_MFC_WriteBit(0x2A18, 0, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
570 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
618 MDrv_MFC_WriteBit(0x30A0, 1, _BIT1);
765 MDrv_MFC_WriteBit(0x2080, _DISABLE, _BIT0); // disable film32 in MDrv_MFC_SetOutDClk()
[all …]
H A Dmdrv_mfc_scalerip.c128 MDrv_MFC_WriteBit(0x2005, 1, _BIT5); in MDrv_MFC_IP_SetMemMode()
147 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); in MDrv_MFC_InitializeRx()
152 MDrv_MFC_WriteBit(0x2214, 1, _BIT2); //LVDS in MDrv_MFC_InitializeRx()
156 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); //TTL in MDrv_MFC_InitializeRx()
159 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); //TTL in MDrv_MFC_InitializeRx()
161 MDrv_MFC_WriteBit(0x2214, 1, _BIT3); in MDrv_MFC_InitializeRx()
162 MDrv_MFC_WriteBit(0x2214, 1, _BIT5); in MDrv_MFC_InitializeRx()
164 MDrv_MFC_WriteBit(0x2216, 1, _BIT3); in MDrv_MFC_InitializeRx()
165 MDrv_MFC_WriteBit(0x2216, 1, _BIT4); in MDrv_MFC_InitializeRx()
167 MDrv_MFC_WriteBit(0x221E, 1, _BIT3); in MDrv_MFC_InitializeRx()
[all …]
H A Dmdrv_mfc_mcu.c108 MDrv_MFC_WriteBit(0x3C66, 1, _BIT1); // XD_MCU1[0xC0] = 0; in MDrv_MFC_McuWatchDogClear()
130 MDrv_MFC_WriteBit(0x1018, 1, _BIT3); in MDrv_MFC_McuICacheCtrl()
131 MDrv_MFC_WriteBit(0x2BA0, 0, _BIT0); in MDrv_MFC_McuICacheCtrl()
135 MDrv_MFC_WriteBit(0x1018, 0, _BIT3); in MDrv_MFC_McuICacheCtrl()
136 MDrv_MFC_WriteBit(0x2BA0, 1, _BIT0); in MDrv_MFC_McuICacheCtrl()
171 MDrv_MFC_WriteBit(0x1E06, bEnable, _BIT5); // [0] in MDrv_MFC_McuUsePLL()
202 MDrv_MFC_WriteBit(0x2401, 0, _BIT0); // Vsync change irq in MDrv_MFC_SetInterrupt()
203 MDrv_MFC_WriteBit(0x2406, 0, _BIT1); // OP Vsync irq in MDrv_MFC_SetInterrupt()
204 MDrv_MFC_WriteBit(0x2406, 0, _BIT3); // end of DE irq in MDrv_MFC_SetInterrupt()
212 MDrv_MFC_WriteBit(0x2401, 1, _BIT0); // Vsync change irq in MDrv_MFC_SetInterrupt()
[all …]
H A Dmdrv_mfc_panel.c566 MDrv_MFC_WriteBit(0x20C0, gmfcSysInfo.u8PanelCSC, _BIT0); // [0]:CSC [1]:dither [2]:round in msInitializeColorMatrix()
587 MDrv_MFC_WriteBit(0x23F0, 1, _BIT3);//reg_ctrl_low_sel-----I-Chang 0909 in msInitializeTcon()
588 MDrv_MFC_WriteBit(0x23F0, 1, _BIT2);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
589 MDrv_MFC_WriteBit(0x23F0, 0, _BIT1);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
590 MDrv_MFC_WriteBit(0x23F0, 0, _BIT0);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
591 MDrv_MFC_WriteBit(0x2313, 1, _BIT7);//reg_tp_md_sel-----I-Chang 0909 in msInitializeTcon()
592 MDrv_MFC_WriteBit(0x230F, 1, _BIT3);//Request by Bryan, control load-----I-Chang 0901 in msInitializeTcon()
595 MDrv_MFC_WriteBit(0x238C, 0, _BIT0); //Output Enable FLK //j081031 in msInitializeTcon()
606 MDrv_MFC_WriteBit(0x2052, 0, _BIT0);//Only for visit; PC mode on-----I-Chang 0829 in msInitializeTcon()
608 MDrv_MFC_WriteBit(0x2300, gmfcSysInfo.u8PanelBlankCPVC, _BIT6); in msInitializeTcon()
[all …]
/utopia/UTPA2-700.0.x/modules/mfc/hal/M7821/mfc/
H A Dmdrv_mfc_scalerop.c288 MDrv_MFC_WriteBit(0x2A2C, 1, _BIT0); in MDrv_MFC_SetVCO()
303 MDrv_MFC_WriteBit(0x2A1B, _ENABLE, _BIT3); in MDrv_MFC_SetLvdsSSC()
322 MDrv_MFC_WriteBit(0x2A1B, _DISABLE, _BIT3); in MDrv_MFC_SetLvdsSSC()
482 MDrv_MFC_WriteBit(0x2A2C, 1, _BIT0); in msLPLL_SetVCO()
499 MDrv_MFC_WriteBit(0x2080, _DISABLE, _BIT0); // disable film32 in msSetOutDClk()
503 MDrv_MFC_WriteBit(0x2080, _ENABLE, _BIT0); // enable film32 in msSetOutDClk()
506 MDrv_MFC_WriteBit(0x2A18, 0, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
570 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
618 MDrv_MFC_WriteBit(0x30A0, 1, _BIT1);
765 MDrv_MFC_WriteBit(0x2080, _DISABLE, _BIT0); // disable film32 in MDrv_MFC_SetOutDClk()
[all …]
H A Dmdrv_mfc_scalerip.c128 MDrv_MFC_WriteBit(0x2005, 1, _BIT5); in MDrv_MFC_IP_SetMemMode()
147 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); in MDrv_MFC_InitializeRx()
152 MDrv_MFC_WriteBit(0x2214, 1, _BIT2); //LVDS in MDrv_MFC_InitializeRx()
156 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); //TTL in MDrv_MFC_InitializeRx()
159 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); //TTL in MDrv_MFC_InitializeRx()
161 MDrv_MFC_WriteBit(0x2214, 1, _BIT3); in MDrv_MFC_InitializeRx()
162 MDrv_MFC_WriteBit(0x2214, 1, _BIT5); in MDrv_MFC_InitializeRx()
164 MDrv_MFC_WriteBit(0x2216, 1, _BIT3); in MDrv_MFC_InitializeRx()
165 MDrv_MFC_WriteBit(0x2216, 1, _BIT4); in MDrv_MFC_InitializeRx()
167 MDrv_MFC_WriteBit(0x221E, 1, _BIT3); in MDrv_MFC_InitializeRx()
[all …]
H A Dmdrv_mfc_mcu.c108 MDrv_MFC_WriteBit(0x3C66, 1, _BIT1); // XD_MCU1[0xC0] = 0; in MDrv_MFC_McuWatchDogClear()
130 MDrv_MFC_WriteBit(0x1018, 1, _BIT3); in MDrv_MFC_McuICacheCtrl()
131 MDrv_MFC_WriteBit(0x2BA0, 0, _BIT0); in MDrv_MFC_McuICacheCtrl()
135 MDrv_MFC_WriteBit(0x1018, 0, _BIT3); in MDrv_MFC_McuICacheCtrl()
136 MDrv_MFC_WriteBit(0x2BA0, 1, _BIT0); in MDrv_MFC_McuICacheCtrl()
171 MDrv_MFC_WriteBit(0x1E06, bEnable, _BIT5); // [0] in MDrv_MFC_McuUsePLL()
202 MDrv_MFC_WriteBit(0x2401, 0, _BIT0); // Vsync change irq in MDrv_MFC_SetInterrupt()
203 MDrv_MFC_WriteBit(0x2406, 0, _BIT1); // OP Vsync irq in MDrv_MFC_SetInterrupt()
204 MDrv_MFC_WriteBit(0x2406, 0, _BIT3); // end of DE irq in MDrv_MFC_SetInterrupt()
212 MDrv_MFC_WriteBit(0x2401, 1, _BIT0); // Vsync change irq in MDrv_MFC_SetInterrupt()
[all …]
H A Dmdrv_mfc_panel.c566 MDrv_MFC_WriteBit(0x20C0, gmfcSysInfo.u8PanelCSC, _BIT0); // [0]:CSC [1]:dither [2]:round in msInitializeColorMatrix()
587 MDrv_MFC_WriteBit(0x23F0, 1, _BIT3);//reg_ctrl_low_sel-----I-Chang 0909 in msInitializeTcon()
588 MDrv_MFC_WriteBit(0x23F0, 1, _BIT2);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
589 MDrv_MFC_WriteBit(0x23F0, 0, _BIT1);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
590 MDrv_MFC_WriteBit(0x23F0, 0, _BIT0);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
591 MDrv_MFC_WriteBit(0x2313, 1, _BIT7);//reg_tp_md_sel-----I-Chang 0909 in msInitializeTcon()
592 MDrv_MFC_WriteBit(0x230F, 1, _BIT3);//Request by Bryan, control load-----I-Chang 0901 in msInitializeTcon()
595 MDrv_MFC_WriteBit(0x238C, 0, _BIT0); //Output Enable FLK //j081031 in msInitializeTcon()
606 MDrv_MFC_WriteBit(0x2052, 0, _BIT0);//Only for visit; PC mode on-----I-Chang 0829 in msInitializeTcon()
608 MDrv_MFC_WriteBit(0x2300, gmfcSysInfo.u8PanelBlankCPVC, _BIT6); in msInitializeTcon()
[all …]
/utopia/UTPA2-700.0.x/modules/mfc/hal/maxim/mfc/
H A Dmdrv_mfc_scalerop.c288 MDrv_MFC_WriteBit(0x2A2C, 1, _BIT0); in MDrv_MFC_SetVCO()
303 MDrv_MFC_WriteBit(0x2A1B, _ENABLE, _BIT3); in MDrv_MFC_SetLvdsSSC()
322 MDrv_MFC_WriteBit(0x2A1B, _DISABLE, _BIT3); in MDrv_MFC_SetLvdsSSC()
482 MDrv_MFC_WriteBit(0x2A2C, 1, _BIT0); in msLPLL_SetVCO()
499 MDrv_MFC_WriteBit(0x2080, _DISABLE, _BIT0); // disable film32 in msSetOutDClk()
503 MDrv_MFC_WriteBit(0x2080, _ENABLE, _BIT0); // enable film32 in msSetOutDClk()
506 MDrv_MFC_WriteBit(0x2A18, 0, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
570 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
618 MDrv_MFC_WriteBit(0x30A0, 1, _BIT1);
765 MDrv_MFC_WriteBit(0x2080, _DISABLE, _BIT0); // disable film32 in MDrv_MFC_SetOutDClk()
[all …]
H A Dmdrv_mfc_scalerip.c128 MDrv_MFC_WriteBit(0x2005, 1, _BIT5); in MDrv_MFC_IP_SetMemMode()
147 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); in MDrv_MFC_InitializeRx()
152 MDrv_MFC_WriteBit(0x2214, 1, _BIT2); //LVDS in MDrv_MFC_InitializeRx()
156 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); //TTL in MDrv_MFC_InitializeRx()
159 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); //TTL in MDrv_MFC_InitializeRx()
161 MDrv_MFC_WriteBit(0x2214, 1, _BIT3); in MDrv_MFC_InitializeRx()
162 MDrv_MFC_WriteBit(0x2214, 1, _BIT5); in MDrv_MFC_InitializeRx()
164 MDrv_MFC_WriteBit(0x2216, 1, _BIT3); in MDrv_MFC_InitializeRx()
165 MDrv_MFC_WriteBit(0x2216, 1, _BIT4); in MDrv_MFC_InitializeRx()
167 MDrv_MFC_WriteBit(0x221E, 1, _BIT3); in MDrv_MFC_InitializeRx()
[all …]
H A Dmdrv_mfc_mcu.c108 MDrv_MFC_WriteBit(0x3C66, 1, _BIT1); // XD_MCU1[0xC0] = 0; in MDrv_MFC_McuWatchDogClear()
130 MDrv_MFC_WriteBit(0x1018, 1, _BIT3); in MDrv_MFC_McuICacheCtrl()
131 MDrv_MFC_WriteBit(0x2BA0, 0, _BIT0); in MDrv_MFC_McuICacheCtrl()
135 MDrv_MFC_WriteBit(0x1018, 0, _BIT3); in MDrv_MFC_McuICacheCtrl()
136 MDrv_MFC_WriteBit(0x2BA0, 1, _BIT0); in MDrv_MFC_McuICacheCtrl()
171 MDrv_MFC_WriteBit(0x1E06, bEnable, _BIT5); // [0] in MDrv_MFC_McuUsePLL()
202 MDrv_MFC_WriteBit(0x2401, 0, _BIT0); // Vsync change irq in MDrv_MFC_SetInterrupt()
203 MDrv_MFC_WriteBit(0x2406, 0, _BIT1); // OP Vsync irq in MDrv_MFC_SetInterrupt()
204 MDrv_MFC_WriteBit(0x2406, 0, _BIT3); // end of DE irq in MDrv_MFC_SetInterrupt()
212 MDrv_MFC_WriteBit(0x2401, 1, _BIT0); // Vsync change irq in MDrv_MFC_SetInterrupt()
[all …]
H A Dmdrv_mfc_panel.c566 MDrv_MFC_WriteBit(0x20C0, gmfcSysInfo.u8PanelCSC, _BIT0); // [0]:CSC [1]:dither [2]:round in msInitializeColorMatrix()
587 MDrv_MFC_WriteBit(0x23F0, 1, _BIT3);//reg_ctrl_low_sel-----I-Chang 0909 in msInitializeTcon()
588 MDrv_MFC_WriteBit(0x23F0, 1, _BIT2);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
589 MDrv_MFC_WriteBit(0x23F0, 0, _BIT1);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
590 MDrv_MFC_WriteBit(0x23F0, 0, _BIT0);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
591 MDrv_MFC_WriteBit(0x2313, 1, _BIT7);//reg_tp_md_sel-----I-Chang 0909 in msInitializeTcon()
592 MDrv_MFC_WriteBit(0x230F, 1, _BIT3);//Request by Bryan, control load-----I-Chang 0901 in msInitializeTcon()
595 MDrv_MFC_WriteBit(0x238C, 0, _BIT0); //Output Enable FLK //j081031 in msInitializeTcon()
606 MDrv_MFC_WriteBit(0x2052, 0, _BIT0);//Only for visit; PC mode on-----I-Chang 0829 in msInitializeTcon()
608 MDrv_MFC_WriteBit(0x2300, gmfcSysInfo.u8PanelBlankCPVC, _BIT6); in msInitializeTcon()
[all …]
/utopia/UTPA2-700.0.x/modules/mfc/hal/manhattan/mfc/
H A Dmdrv_mfc_scalerop.c288 MDrv_MFC_WriteBit(0x2A2C, 1, _BIT0); in MDrv_MFC_SetVCO()
303 MDrv_MFC_WriteBit(0x2A1B, _ENABLE, _BIT3); in MDrv_MFC_SetLvdsSSC()
322 MDrv_MFC_WriteBit(0x2A1B, _DISABLE, _BIT3); in MDrv_MFC_SetLvdsSSC()
482 MDrv_MFC_WriteBit(0x2A2C, 1, _BIT0); in msLPLL_SetVCO()
499 MDrv_MFC_WriteBit(0x2080, _DISABLE, _BIT0); // disable film32 in msSetOutDClk()
503 MDrv_MFC_WriteBit(0x2080, _ENABLE, _BIT0); // enable film32 in msSetOutDClk()
506 MDrv_MFC_WriteBit(0x2A18, 0, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
570 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
618 MDrv_MFC_WriteBit(0x30A0, 1, _BIT1);
765 MDrv_MFC_WriteBit(0x2080, _DISABLE, _BIT0); // disable film32 in MDrv_MFC_SetOutDClk()
[all …]
H A Dmdrv_mfc_scalerip.c128 MDrv_MFC_WriteBit(0x2005, 1, _BIT5); in MDrv_MFC_IP_SetMemMode()
147 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); in MDrv_MFC_InitializeRx()
152 MDrv_MFC_WriteBit(0x2214, 1, _BIT2); //LVDS in MDrv_MFC_InitializeRx()
156 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); //TTL in MDrv_MFC_InitializeRx()
159 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); //TTL in MDrv_MFC_InitializeRx()
161 MDrv_MFC_WriteBit(0x2214, 1, _BIT3); in MDrv_MFC_InitializeRx()
162 MDrv_MFC_WriteBit(0x2214, 1, _BIT5); in MDrv_MFC_InitializeRx()
164 MDrv_MFC_WriteBit(0x2216, 1, _BIT3); in MDrv_MFC_InitializeRx()
165 MDrv_MFC_WriteBit(0x2216, 1, _BIT4); in MDrv_MFC_InitializeRx()
167 MDrv_MFC_WriteBit(0x221E, 1, _BIT3); in MDrv_MFC_InitializeRx()
[all …]
H A Dmdrv_mfc_mcu.c108 MDrv_MFC_WriteBit(0x3C66, 1, _BIT1); // XD_MCU1[0xC0] = 0; in MDrv_MFC_McuWatchDogClear()
130 MDrv_MFC_WriteBit(0x1018, 1, _BIT3); in MDrv_MFC_McuICacheCtrl()
131 MDrv_MFC_WriteBit(0x2BA0, 0, _BIT0); in MDrv_MFC_McuICacheCtrl()
135 MDrv_MFC_WriteBit(0x1018, 0, _BIT3); in MDrv_MFC_McuICacheCtrl()
136 MDrv_MFC_WriteBit(0x2BA0, 1, _BIT0); in MDrv_MFC_McuICacheCtrl()
171 MDrv_MFC_WriteBit(0x1E06, bEnable, _BIT5); // [0] in MDrv_MFC_McuUsePLL()
202 MDrv_MFC_WriteBit(0x2401, 0, _BIT0); // Vsync change irq in MDrv_MFC_SetInterrupt()
203 MDrv_MFC_WriteBit(0x2406, 0, _BIT1); // OP Vsync irq in MDrv_MFC_SetInterrupt()
204 MDrv_MFC_WriteBit(0x2406, 0, _BIT3); // end of DE irq in MDrv_MFC_SetInterrupt()
212 MDrv_MFC_WriteBit(0x2401, 1, _BIT0); // Vsync change irq in MDrv_MFC_SetInterrupt()
[all …]
H A Dmdrv_mfc_panel.c566 MDrv_MFC_WriteBit(0x20C0, gmfcSysInfo.u8PanelCSC, _BIT0); // [0]:CSC [1]:dither [2]:round in msInitializeColorMatrix()
587 MDrv_MFC_WriteBit(0x23F0, 1, _BIT3);//reg_ctrl_low_sel-----I-Chang 0909 in msInitializeTcon()
588 MDrv_MFC_WriteBit(0x23F0, 1, _BIT2);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
589 MDrv_MFC_WriteBit(0x23F0, 0, _BIT1);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
590 MDrv_MFC_WriteBit(0x23F0, 0, _BIT0);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
591 MDrv_MFC_WriteBit(0x2313, 1, _BIT7);//reg_tp_md_sel-----I-Chang 0909 in msInitializeTcon()
592 MDrv_MFC_WriteBit(0x230F, 1, _BIT3);//Request by Bryan, control load-----I-Chang 0901 in msInitializeTcon()
595 MDrv_MFC_WriteBit(0x238C, 0, _BIT0); //Output Enable FLK //j081031 in msInitializeTcon()
606 MDrv_MFC_WriteBit(0x2052, 0, _BIT0);//Only for visit; PC mode on-----I-Chang 0829 in msInitializeTcon()
608 MDrv_MFC_WriteBit(0x2300, gmfcSysInfo.u8PanelBlankCPVC, _BIT6); in msInitializeTcon()
[all …]
/utopia/UTPA2-700.0.x/modules/mfc/hal/M7621/mfc/
H A Dmdrv_mfc_scalerop.c288 MDrv_MFC_WriteBit(0x2A2C, 1, _BIT0); in MDrv_MFC_SetVCO()
303 MDrv_MFC_WriteBit(0x2A1B, _ENABLE, _BIT3); in MDrv_MFC_SetLvdsSSC()
322 MDrv_MFC_WriteBit(0x2A1B, _DISABLE, _BIT3); in MDrv_MFC_SetLvdsSSC()
482 MDrv_MFC_WriteBit(0x2A2C, 1, _BIT0); in msLPLL_SetVCO()
499 MDrv_MFC_WriteBit(0x2080, _DISABLE, _BIT0); // disable film32 in msSetOutDClk()
503 MDrv_MFC_WriteBit(0x2080, _ENABLE, _BIT0); // enable film32 in msSetOutDClk()
506 MDrv_MFC_WriteBit(0x2A18, 0, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
570 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
618 MDrv_MFC_WriteBit(0x30A0, 1, _BIT1);
765 MDrv_MFC_WriteBit(0x2080, _DISABLE, _BIT0); // disable film32 in MDrv_MFC_SetOutDClk()
[all …]
H A Dmdrv_mfc_scalerip.c128 MDrv_MFC_WriteBit(0x2005, 1, _BIT5); in MDrv_MFC_IP_SetMemMode()
147 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); in MDrv_MFC_InitializeRx()
152 MDrv_MFC_WriteBit(0x2214, 1, _BIT2); //LVDS in MDrv_MFC_InitializeRx()
156 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); //TTL in MDrv_MFC_InitializeRx()
159 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); //TTL in MDrv_MFC_InitializeRx()
161 MDrv_MFC_WriteBit(0x2214, 1, _BIT3); in MDrv_MFC_InitializeRx()
162 MDrv_MFC_WriteBit(0x2214, 1, _BIT5); in MDrv_MFC_InitializeRx()
164 MDrv_MFC_WriteBit(0x2216, 1, _BIT3); in MDrv_MFC_InitializeRx()
165 MDrv_MFC_WriteBit(0x2216, 1, _BIT4); in MDrv_MFC_InitializeRx()
167 MDrv_MFC_WriteBit(0x221E, 1, _BIT3); in MDrv_MFC_InitializeRx()
[all …]
H A Dmdrv_mfc_mcu.c108 MDrv_MFC_WriteBit(0x3C66, 1, _BIT1); // XD_MCU1[0xC0] = 0; in MDrv_MFC_McuWatchDogClear()
130 MDrv_MFC_WriteBit(0x1018, 1, _BIT3); in MDrv_MFC_McuICacheCtrl()
131 MDrv_MFC_WriteBit(0x2BA0, 0, _BIT0); in MDrv_MFC_McuICacheCtrl()
135 MDrv_MFC_WriteBit(0x1018, 0, _BIT3); in MDrv_MFC_McuICacheCtrl()
136 MDrv_MFC_WriteBit(0x2BA0, 1, _BIT0); in MDrv_MFC_McuICacheCtrl()
171 MDrv_MFC_WriteBit(0x1E06, bEnable, _BIT5); // [0] in MDrv_MFC_McuUsePLL()
202 MDrv_MFC_WriteBit(0x2401, 0, _BIT0); // Vsync change irq in MDrv_MFC_SetInterrupt()
203 MDrv_MFC_WriteBit(0x2406, 0, _BIT1); // OP Vsync irq in MDrv_MFC_SetInterrupt()
204 MDrv_MFC_WriteBit(0x2406, 0, _BIT3); // end of DE irq in MDrv_MFC_SetInterrupt()
212 MDrv_MFC_WriteBit(0x2401, 1, _BIT0); // Vsync change irq in MDrv_MFC_SetInterrupt()
[all …]
H A Dmdrv_mfc_panel.c566 MDrv_MFC_WriteBit(0x20C0, gmfcSysInfo.u8PanelCSC, _BIT0); // [0]:CSC [1]:dither [2]:round in msInitializeColorMatrix()
587 MDrv_MFC_WriteBit(0x23F0, 1, _BIT3);//reg_ctrl_low_sel-----I-Chang 0909 in msInitializeTcon()
588 MDrv_MFC_WriteBit(0x23F0, 1, _BIT2);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
589 MDrv_MFC_WriteBit(0x23F0, 0, _BIT1);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
590 MDrv_MFC_WriteBit(0x23F0, 0, _BIT0);//reg_de_delay-----I-Chang 0909 in msInitializeTcon()
591 MDrv_MFC_WriteBit(0x2313, 1, _BIT7);//reg_tp_md_sel-----I-Chang 0909 in msInitializeTcon()
592 MDrv_MFC_WriteBit(0x230F, 1, _BIT3);//Request by Bryan, control load-----I-Chang 0901 in msInitializeTcon()
595 MDrv_MFC_WriteBit(0x238C, 0, _BIT0); //Output Enable FLK //j081031 in msInitializeTcon()
606 MDrv_MFC_WriteBit(0x2052, 0, _BIT0);//Only for visit; PC mode on-----I-Chang 0829 in msInitializeTcon()
608 MDrv_MFC_WriteBit(0x2300, gmfcSysInfo.u8PanelBlankCPVC, _BIT6); in msInitializeTcon()
[all …]

12