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Searched refs:L_CLKGEN2 (Results 1 – 14 of 14) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.h207 #define L_CLKGEN2(x) BK_REG_L(REG_RVD_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A DhalPNL.h209 #define L_CLKGEN2(x) BK_REG_L(REG_RVD_BASE, x) macro
H A DhalPNL.c5255 W2BYTEMSK(L_CLKGEN2(CLKGEN2SettingTBL_Video[u8CLKTblIndex][indexCounter].address), in _MHal_PNL_DumpVideoClkTable()
5302 W2BYTEMSK(L_CLKGEN2(CLKGEN2SettingTBL_OSD[u8CLKTblIndex][indexCounter].address), in _MHal_PNL_DumpOSDClkTable()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A DhalPNL.h209 #define L_CLKGEN2(x) BK_REG_L(REG_RVD_BASE, x) macro
H A DhalPNL.c5305 W2BYTEMSK(L_CLKGEN2(CLKGEN2SettingTBL_Video[u8CLKTblIndex][indexCounter].address), in _MHal_PNL_DumpVideoClkTable()
5352 W2BYTEMSK(L_CLKGEN2(CLKGEN2SettingTBL_OSD[u8CLKTblIndex][indexCounter].address), in _MHal_PNL_DumpOSDClkTable()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A DhalPNL.h207 #define L_CLKGEN2(x) BK_REG_L(REG_RVD_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h657 #define L_CLKGEN2(x) BK_REG_L(REG_CLKGEN2_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h669 #define L_CLKGEN2(x) BK_REG_L(REG_CLKGEN2_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h674 #define L_CLKGEN2(x) BK_REG_L(REG_CLKGEN2_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h661 #define L_CLKGEN2(x) BK_REG_L(REG_CLKGEN2_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_sc.c6375 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0C00); // 354MHz in MHal_CLKGEN_FRC_Init()
6376 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
6377 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
6385 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0C00); // 192MHz --> use 354MHz by mike-hh in MHal_CLKGEN_FRC_Init()
6386 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
6387 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
10535 W2BYTEMSK(L_CLKGEN2(0x44),0x0100,0x0100); // BK100A_CKGEN2_44[8] in MHal_XC_SRAM_PowerDown_Control()
10571 W2BYTEMSK(L_CLKGEN2(0x44),0x0000,0x0100); // BK100A_CKGEN2_44[8] in MHal_XC_SRAM_PowerDown_Control()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_sc.c6375 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0C00); // 354MHz in MHal_CLKGEN_FRC_Init()
6376 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
6377 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
6385 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0C00); // 192MHz --> use 354MHz by mike-hh in MHal_CLKGEN_FRC_Init()
6386 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
6387 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
10507 W2BYTEMSK(L_CLKGEN2(0x44),0x0100,0x0100); // BK100A_CKGEN2_44[8] in MHal_XC_SRAM_PowerDown_Control()
10543 W2BYTEMSK(L_CLKGEN2(0x44),0x0000,0x0100); // BK100A_CKGEN2_44[8] in MHal_XC_SRAM_PowerDown_Control()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_sc.c6074 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0C00); // 192MHz --> use 354MHz by mike-hh in MHal_CLKGEN_FRC_Init()
6075 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
6076 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
10253 W2BYTEMSK(L_CLKGEN2(0x44),0x0100,0x0100); // BK100A_CKGEN2_44[8] in MHal_XC_SRAM_PowerDown_Control()
10290 W2BYTEMSK(L_CLKGEN2(0x44),0x0000,0x0100); // BK100A_CKGEN2_44[8] in MHal_XC_SRAM_PowerDown_Control()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_sc.c6094 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0C00); // 192MHz --> use 354MHz by mike-hh in MHal_CLKGEN_FRC_Init()
6095 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0200); // Not Invert in MHal_CLKGEN_FRC_Init()
6096 W2BYTEMSK(L_CLKGEN2(0x44), 0x0000, 0x0100); // Enable clock in MHal_CLKGEN_FRC_Init()
10225 W2BYTEMSK(L_CLKGEN2(0x44),0x0100,0x0100); // BK100A_CKGEN2_44[8] in MHal_XC_SRAM_PowerDown_Control()
10262 W2BYTEMSK(L_CLKGEN2(0x44),0x0000,0x0100); // BK100A_CKGEN2_44[8] in MHal_XC_SRAM_PowerDown_Control()