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Searched refs:L_BK_ADC_ATOP (Results 1 – 25 of 59) sorted by relevance

123

/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_offline.c227 W2BYTEMSK(L_BK_ADC_ATOP(0x3C), 0, BIT(13) ); in Hal_XC_SetOffLineToSog_AV()
229 W2BYTEMSK(L_BK_ADC_ATOP(0x3C), BIT(13), BIT(13) ); in Hal_XC_SetOffLineToSog_AV()
233 MDrv_Write2Byte(L_BK_ADC_ATOP(0x04), 0); in Hal_XC_SetOffLineToSog_AV()
234 MDrv_Write2Byte(L_BK_ADC_ATOP(0x05), 0); in Hal_XC_SetOffLineToSog_AV()
235 MDrv_Write2Byte(L_BK_ADC_ATOP(0x06), 0); in Hal_XC_SetOffLineToSog_AV()
236 MDrv_Write2ByteMask(L_BK_ADC_ATOP(0x5e), 0, 0x3fc); in Hal_XC_SetOffLineToSog_AV()
237 … MDrv_WriteByte(L_BK_ADC_ATOP(0x3d), (MDrv_ReadByte(L_BK_ADC_ATOP(0x3d)) & 0xf0) | (Channel + 3)); in Hal_XC_SetOffLineToSog_AV()
245 W2BYTEMSK(L_BK_ADC_ATOP(0x3C), 0, BIT(13) ); in Hal_XC_SetOffLineToSog_YUV()
247 W2BYTEMSK(L_BK_ADC_ATOP(0x3C), BIT(13), BIT(13) ); in Hal_XC_SetOffLineToSog_YUV()
251 MDrv_Write2Byte(L_BK_ADC_ATOP(0x04), 0); in Hal_XC_SetOffLineToSog_YUV()
[all …]
H A Dmhal_adc.c821 W2BYTEMSK(L_BK_ADC_ATOP(0x5B) , BIT(13), BIT(13)); in _Hal_ADC_Set_RGBYPbPr_Calibration()
822 W2BYTEMSK(L_BK_ADC_ATOP(0x5B) ,((MS_U16)efuseBandgap & 0x1F) << 8, BMASK(12:8) ); in _Hal_ADC_Set_RGBYPbPr_Calibration()
832 W2BYTEMSK(L_BK_ADC_ATOP(0x5B) , 0, BIT(13)); in _Hal_ADC_Set_RGBYPbPr_Calibration()
1338 MDrv_Write2Byte(L_BK_ADC_ATOP(0x00) ,0x0001 ); in Hal_ADC_InitInternalCalibration()
1353 MDrv_Write2Byte(L_BK_ADC_ATOP(0x04) ,0xF800 ); in Hal_ADC_InitInternalCalibration()
1354 MDrv_Write2Byte(L_BK_ADC_ATOP(0x05) ,0x0003 ); in Hal_ADC_InitInternalCalibration()
1355 MDrv_Write2Byte(L_BK_ADC_ATOP(0x06) ,0xFB00 ); in Hal_ADC_InitInternalCalibration()
1377 MDrv_Write2Byte(L_BK_ADC_ATOP(0x03) ,0x0000 ); in Hal_ADC_InitInternalCalibration()
1378 MDrv_Write2Byte(L_BK_ADC_ATOP(0x5E) ,0x0200); in Hal_ADC_InitInternalCalibration()
2354 _stAutoAdcSetting.u8L_BkAtop_00 = MDrv_ReadByte(L_BK_ADC_ATOP(0x00) ); in Hal_ADC_auto_adc_backup()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_offline.c227 W2BYTEMSK(L_BK_ADC_ATOP(0x3C), 0, BIT(13) ); in Hal_XC_SetOffLineToSog_AV()
229 W2BYTEMSK(L_BK_ADC_ATOP(0x3C), BIT(13), BIT(13) ); in Hal_XC_SetOffLineToSog_AV()
233 MDrv_Write2Byte(L_BK_ADC_ATOP(0x04), 0); in Hal_XC_SetOffLineToSog_AV()
234 MDrv_Write2Byte(L_BK_ADC_ATOP(0x05), 0); in Hal_XC_SetOffLineToSog_AV()
235 MDrv_Write2Byte(L_BK_ADC_ATOP(0x06), 0); in Hal_XC_SetOffLineToSog_AV()
236 MDrv_Write2ByteMask(L_BK_ADC_ATOP(0x5e), 0, 0x3fc); in Hal_XC_SetOffLineToSog_AV()
237 … MDrv_WriteByte(L_BK_ADC_ATOP(0x3d), (MDrv_ReadByte(L_BK_ADC_ATOP(0x3d)) & 0xf0) | (Channel + 3)); in Hal_XC_SetOffLineToSog_AV()
245 W2BYTEMSK(L_BK_ADC_ATOP(0x3C), 0, BIT(13) ); in Hal_XC_SetOffLineToSog_YUV()
247 W2BYTEMSK(L_BK_ADC_ATOP(0x3C), BIT(13), BIT(13) ); in Hal_XC_SetOffLineToSog_YUV()
251 MDrv_Write2Byte(L_BK_ADC_ATOP(0x04), 0); in Hal_XC_SetOffLineToSog_YUV()
[all …]
H A Dmhal_adc.c821 W2BYTEMSK(L_BK_ADC_ATOP(0x5B) , BIT(13), BIT(13)); in _Hal_ADC_Set_RGBYPbPr_Calibration()
822 W2BYTEMSK(L_BK_ADC_ATOP(0x5B) ,((MS_U16)efuseBandgap & 0x1F) << 8, BMASK(12:8) ); in _Hal_ADC_Set_RGBYPbPr_Calibration()
832 W2BYTEMSK(L_BK_ADC_ATOP(0x5B) , 0, BIT(13)); in _Hal_ADC_Set_RGBYPbPr_Calibration()
1338 MDrv_Write2Byte(L_BK_ADC_ATOP(0x00) ,0x0001 ); in Hal_ADC_InitInternalCalibration()
1353 MDrv_Write2Byte(L_BK_ADC_ATOP(0x04) ,0xF800 ); in Hal_ADC_InitInternalCalibration()
1354 MDrv_Write2Byte(L_BK_ADC_ATOP(0x05) ,0x0003 ); in Hal_ADC_InitInternalCalibration()
1355 MDrv_Write2Byte(L_BK_ADC_ATOP(0x06) ,0xFB00 ); in Hal_ADC_InitInternalCalibration()
1377 MDrv_Write2Byte(L_BK_ADC_ATOP(0x03) ,0x0000 ); in Hal_ADC_InitInternalCalibration()
1378 MDrv_Write2Byte(L_BK_ADC_ATOP(0x5E) ,0x0200); in Hal_ADC_InitInternalCalibration()
2354 _stAutoAdcSetting.u8L_BkAtop_00 = MDrv_ReadByte(L_BK_ADC_ATOP(0x00) ); in Hal_ADC_auto_adc_backup()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/
H A DhalAVD.c3467 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClock()
3468 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7))); in HAL_AVD_AFEC_SetClock()
3476 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0xFF, (BIT(1))); in HAL_AVD_AFEC_SetClock()
3477 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0xFF, (BIT(7))); in HAL_AVD_AFEC_SetClock()
3509 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R… in HAL_AVD_AFEC_SetClockSource()
3510 RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB in HAL_AVD_AFEC_SetClockSource()
3512 RIU_WriteByteMask(L_BK_ADC_ATOP(0x04), 0x00, (BIT(3)|BIT(2)|BIT(1)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
3514 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClockSource()
3515 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
3520 RIU_WriteByte(L_BK_ADC_ATOP(0x04), 0xE0); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/
H A DhalAVD.c6823 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6824 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6832 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0xFF, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6833 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0xFF, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6865 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R… in HAL_AVD_AFEC_SetClockSource()
6866 RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB in HAL_AVD_AFEC_SetClockSource()
6868 RIU_WriteByteMask(L_BK_ADC_ATOP(0x04), 0x00, (BIT(3)|BIT(2)|BIT(1)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6870 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClockSource()
6871 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6876 RIU_WriteByte(L_BK_ADC_ATOP(0x04), 0xE0); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/
H A DhalAVD.c6887 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6888 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6901 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0xFF, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6902 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0xFF, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6986 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R… in HAL_AVD_AFEC_SetClockSource()
6987 RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB in HAL_AVD_AFEC_SetClockSource()
6989 RIU_WriteByteMask(L_BK_ADC_ATOP(0x04), 0x00, (BIT(3)|BIT(2)|BIT(1)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6991 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClockSource()
6992 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6997 RIU_WriteByte(L_BK_ADC_ATOP(0x04), 0xE0); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/
H A DhalAVD.c6887 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6888 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6901 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0xFF, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6902 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0xFF, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6986 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R… in HAL_AVD_AFEC_SetClockSource()
6987 RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB in HAL_AVD_AFEC_SetClockSource()
6989 RIU_WriteByteMask(L_BK_ADC_ATOP(0x04), 0x00, (BIT(3)|BIT(2)|BIT(1)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6991 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClockSource()
6992 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6997 RIU_WriteByte(L_BK_ADC_ATOP(0x04), 0xE0); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/
H A DhalAVD.c6881 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6882 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6895 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0xFF, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6896 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0xFF, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6933 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R… in HAL_AVD_AFEC_SetClockSource()
6934 RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB in HAL_AVD_AFEC_SetClockSource()
6936 RIU_WriteByteMask(L_BK_ADC_ATOP(0x04), 0x00, (BIT(3)|BIT(2)|BIT(1)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6938 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClockSource()
6939 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6944 RIU_WriteByte(L_BK_ADC_ATOP(0x04), 0xE0); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/
H A DhalAVD.c6887 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6888 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6901 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0xFF, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6902 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0xFF, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6986 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R… in HAL_AVD_AFEC_SetClockSource()
6987 RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB in HAL_AVD_AFEC_SetClockSource()
6989 RIU_WriteByteMask(L_BK_ADC_ATOP(0x04), 0x00, (BIT(3)|BIT(2)|BIT(1)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6991 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClockSource()
6992 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6997 RIU_WriteByte(L_BK_ADC_ATOP(0x04), 0xE0); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/
H A DhalAVD.c6823 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6824 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6832 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0xFF, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6833 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0xFF, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6865 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R… in HAL_AVD_AFEC_SetClockSource()
6866 RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB in HAL_AVD_AFEC_SetClockSource()
6868 RIU_WriteByteMask(L_BK_ADC_ATOP(0x04), 0x00, (BIT(3)|BIT(2)|BIT(1)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6870 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClockSource()
6871 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6876 RIU_WriteByte(L_BK_ADC_ATOP(0x04), 0xE0); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/
H A DhalAVD.c3467 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClock()
3468 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7))); in HAL_AVD_AFEC_SetClock()
3476 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0xFF, (BIT(1))); in HAL_AVD_AFEC_SetClock()
3477 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0xFF, (BIT(7))); in HAL_AVD_AFEC_SetClock()
3509 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R… in HAL_AVD_AFEC_SetClockSource()
3510 RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB in HAL_AVD_AFEC_SetClockSource()
3512 RIU_WriteByteMask(L_BK_ADC_ATOP(0x04), 0x00, (BIT(3)|BIT(2)|BIT(1)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
3514 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClockSource()
3515 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
3520 RIU_WriteByte(L_BK_ADC_ATOP(0x04), 0xE0); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/
H A DhalAVD.c6887 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6888 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6901 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0xFF, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6902 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0xFF, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6986 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R… in HAL_AVD_AFEC_SetClockSource()
6987 RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB in HAL_AVD_AFEC_SetClockSource()
6989 RIU_WriteByteMask(L_BK_ADC_ATOP(0x04), 0x00, (BIT(3)|BIT(2)|BIT(1)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6991 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClockSource()
6992 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6997 RIU_WriteByte(L_BK_ADC_ATOP(0x04), 0xE0); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/
H A DhalAVD.c6887 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6888 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6901 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0xFF, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6902 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0xFF, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6986 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R… in HAL_AVD_AFEC_SetClockSource()
6987 RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB in HAL_AVD_AFEC_SetClockSource()
6989 RIU_WriteByteMask(L_BK_ADC_ATOP(0x04), 0x00, (BIT(3)|BIT(2)|BIT(1)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6991 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClockSource()
6992 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6997 RIU_WriteByte(L_BK_ADC_ATOP(0x04), 0xE0); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/
H A DhalAVD.c3466 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClock()
3467 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7))); in HAL_AVD_AFEC_SetClock()
3475 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0xFF, (BIT(1))); in HAL_AVD_AFEC_SetClock()
3476 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0xFF, (BIT(7))); in HAL_AVD_AFEC_SetClock()
3508 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R… in HAL_AVD_AFEC_SetClockSource()
3509 RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB in HAL_AVD_AFEC_SetClockSource()
3511 RIU_WriteByteMask(L_BK_ADC_ATOP(0x04), 0x00, (BIT(3)|BIT(2)|BIT(1)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
3513 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClockSource()
3514 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
3519 RIU_WriteByte(L_BK_ADC_ATOP(0x04), 0xE0); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/avd/
H A DhalAVD.c6839 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6840 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6848 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0xFF, (BIT(1))); in HAL_AVD_AFEC_SetClock()
6849 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0xFF, (BIT(7))); in HAL_AVD_AFEC_SetClock()
6881 …RIU_WriteRegBit(L_BK_ADC_ATOP(0x00), ENABLE, BIT(3)); //enable adc clock, TODO check with analog R… in HAL_AVD_AFEC_SetClockSource()
6882 RIU_WriteRegBit(L_BK_ADC_ATOP(0x03), ENABLE, BIT(1)); //use ADCPLB in HAL_AVD_AFEC_SetClockSource()
6884 RIU_WriteByteMask(L_BK_ADC_ATOP(0x04), 0x00, (BIT(3)|BIT(2)|BIT(1)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6886 RIU_WriteByteMask(L_BK_ADC_ATOP(0x05), 0x00, (BIT(1))); in HAL_AVD_AFEC_SetClockSource()
6887 RIU_WriteByteMask(L_BK_ADC_ATOP(0x06), 0x00, (BIT(7)|BIT(0))); in HAL_AVD_AFEC_SetClockSource()
6892 RIU_WriteByte(L_BK_ADC_ATOP(0x04), 0xE0); in HAL_AVD_AFEC_SetClockSource()
[all …]
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/vbi/
H A DhalVBI.c601 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x00), 0x09); // enable VD & YPbPr in VBI_CC_YPbPr_Init()
602 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x02), 0xf0|cvbs_no); // (select VD_ymux for CVBS input from Y) in VBI_CC_YPbPr_Init()
603 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x04), 0x00); // enable analog blocks, 04, 05 in VBI_CC_YPbPr_Init()
605 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x05), 0x00); in VBI_CC_YPbPr_Init()
606 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x06), 0x00); // enable ADC clocks in VBI_CC_YPbPr_Init()
607 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x12), 0x01); // VD pll =2X (16Fsc) in VBI_CC_YPbPr_Init()
/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/vbi/
H A DhalVBI.c601 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x00), 0x09); // enable VD & YPbPr in VBI_CC_YPbPr_Init()
602 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x02), 0xf0|cvbs_no); // (select VD_ymux for CVBS input from Y) in VBI_CC_YPbPr_Init()
603 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x04), 0x00); // enable analog blocks, 04, 05 in VBI_CC_YPbPr_Init()
605 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x05), 0x00); in VBI_CC_YPbPr_Init()
606 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x06), 0x00); // enable ADC clocks in VBI_CC_YPbPr_Init()
607 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x12), 0x01); // VD pll =2X (16Fsc) in VBI_CC_YPbPr_Init()
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/vbi/
H A DhalVBI.c601 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x00), 0x09); // enable VD & YPbPr in VBI_CC_YPbPr_Init()
602 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x02), 0xf0|cvbs_no); // (select VD_ymux for CVBS input from Y) in VBI_CC_YPbPr_Init()
603 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x04), 0x00); // enable analog blocks, 04, 05 in VBI_CC_YPbPr_Init()
605 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x05), 0x00); in VBI_CC_YPbPr_Init()
606 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x06), 0x00); // enable ADC clocks in VBI_CC_YPbPr_Init()
607 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x12), 0x01); // VD pll =2X (16Fsc) in VBI_CC_YPbPr_Init()
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/vbi/
H A DhalVBI.c640 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x00), 0x09); // enable VD & YPbPr in VBI_CC_YPbPr_Init()
641 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x02), 0xf0|cvbs_no); // (select VD_ymux for CVBS input from Y) in VBI_CC_YPbPr_Init()
642 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x04), 0x00); // enable analog blocks, 04, 05 in VBI_CC_YPbPr_Init()
644 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x05), 0x00); in VBI_CC_YPbPr_Init()
645 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x06), 0x00); // enable ADC clocks in VBI_CC_YPbPr_Init()
646 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x12), 0x01); // VD pll =2X (16Fsc) in VBI_CC_YPbPr_Init()
/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/vbi/
H A DhalVBI.c640 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x00), 0x09); // enable VD & YPbPr in VBI_CC_YPbPr_Init()
641 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x02), 0xf0|cvbs_no); // (select VD_ymux for CVBS input from Y) in VBI_CC_YPbPr_Init()
642 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x04), 0x00); // enable analog blocks, 04, 05 in VBI_CC_YPbPr_Init()
644 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x05), 0x00); in VBI_CC_YPbPr_Init()
645 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x06), 0x00); // enable ADC clocks in VBI_CC_YPbPr_Init()
646 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x12), 0x01); // VD pll =2X (16Fsc) in VBI_CC_YPbPr_Init()
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/vbi/
H A DhalVBI.c650 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x00), 0x09); // enable VD & YPbPr in VBI_CC_YPbPr_Init()
651 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x02), 0xf0|cvbs_no); // (select VD_ymux for CVBS input from Y) in VBI_CC_YPbPr_Init()
652 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x04), 0x00); // enable analog blocks, 04, 05 in VBI_CC_YPbPr_Init()
654 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x05), 0x00); in VBI_CC_YPbPr_Init()
655 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x06), 0x00); // enable ADC clocks in VBI_CC_YPbPr_Init()
656 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x12), 0x01); // VD pll =2X (16Fsc) in VBI_CC_YPbPr_Init()
/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/vbi/
H A DhalVBI.c651 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x00), 0x09); // enable VD & YPbPr in VBI_CC_YPbPr_Init()
652 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x02), 0xf0|cvbs_no); // (select VD_ymux for CVBS input from Y) in VBI_CC_YPbPr_Init()
653 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x04), 0x00); // enable analog blocks, 04, 05 in VBI_CC_YPbPr_Init()
655 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x05), 0x00); in VBI_CC_YPbPr_Init()
656 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x06), 0x00); // enable ADC clocks in VBI_CC_YPbPr_Init()
657 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x12), 0x01); // VD pll =2X (16Fsc) in VBI_CC_YPbPr_Init()
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/vbi/
H A DhalVBI.c651 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x00), 0x09); // enable VD & YPbPr in VBI_CC_YPbPr_Init()
652 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x02), 0xf0|cvbs_no); // (select VD_ymux for CVBS input from Y) in VBI_CC_YPbPr_Init()
653 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x04), 0x00); // enable analog blocks, 04, 05 in VBI_CC_YPbPr_Init()
655 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x05), 0x00); in VBI_CC_YPbPr_Init()
656 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x06), 0x00); // enable ADC clocks in VBI_CC_YPbPr_Init()
657 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x12), 0x01); // VD pll =2X (16Fsc) in VBI_CC_YPbPr_Init()
/utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/vbi/
H A DhalVBI.c651 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x00), 0x09); // enable VD & YPbPr in VBI_CC_YPbPr_Init()
652 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x02), 0xf0|cvbs_no); // (select VD_ymux for CVBS input from Y) in VBI_CC_YPbPr_Init()
653 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x04), 0x00); // enable analog blocks, 04, 05 in VBI_CC_YPbPr_Init()
655 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x05), 0x00); in VBI_CC_YPbPr_Init()
656 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x06), 0x00); // enable ADC clocks in VBI_CC_YPbPr_Init()
657 HAL_VBI_WriteByte(L_BK_ADC_ATOP(0x12), 0x01); // VD pll =2X (16Fsc) in VBI_CC_YPbPr_Init()

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