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Searched refs:E_XRULE_NUM (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/pq/hal/k6/pq/include/
H A DdrvPQ_Declare.h165 MS_U8 u8PQ_XRule_IP_Num[E_XRULE_NUM];
166 MS_U8 *pXRule_IP_Index[E_XRULE_NUM];
167 MS_U8 *pXRule_Array[E_XRULE_NUM];
H A DdrvPQ_Define.h198 #define E_XRULE_NUM 7 macro
200 #define E_XRULE_NUM 5 macro
/utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/include/
H A DdrvPQ_Declare.h207 MS_U8 u8PQ_XRule_IP_Num[E_XRULE_NUM];
208 MS_U8 *pXRule_IP_Index[E_XRULE_NUM];
209 MS_U8 *pXRule_Array[E_XRULE_NUM];
H A DdrvPQ_Define.h203 #define E_XRULE_NUM 7 macro
205 #define E_XRULE_NUM 5 macro
/utopia/UTPA2-700.0.x/modules/pq/hal/k6lite/pq/include/
H A DdrvPQ_Declare.h165 MS_U8 u8PQ_XRule_IP_Num[E_XRULE_NUM];
166 MS_U8 *pXRule_IP_Index[E_XRULE_NUM];
167 MS_U8 *pXRule_Array[E_XRULE_NUM];
H A DdrvPQ_Define.h198 #define E_XRULE_NUM 7 macro
200 #define E_XRULE_NUM 5 macro
/utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/include/
H A DdrvPQ_Declare.h207 MS_U8 u8PQ_XRule_IP_Num[E_XRULE_NUM];
208 MS_U8 *pXRule_IP_Index[E_XRULE_NUM];
209 MS_U8 *pXRule_Array[E_XRULE_NUM];
H A DdrvPQ_Define.h203 #define E_XRULE_NUM 7 macro
205 #define E_XRULE_NUM 5 macro
/utopia/UTPA2-700.0.x/modules/pq/hal/manhattan/pq/include/
H A DdrvPQ_Declare.h201 MS_U8 u8PQ_XRule_IP_Num[E_XRULE_NUM];
202 MS_U8 *pXRule_IP_Index[E_XRULE_NUM];
203 MS_U8 *pXRule_Array[E_XRULE_NUM];
H A DdrvPQ_Define.h194 #define E_XRULE_NUM 7 macro
196 #define E_XRULE_NUM 5 macro
/utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/include/
H A DdrvPQ_Declare.h208 MS_U8 u8PQ_XRule_IP_Num[E_XRULE_NUM];
209 MS_U8 *pXRule_IP_Index[E_XRULE_NUM];
210 MS_U8 *pXRule_Array[E_XRULE_NUM];
H A DdrvPQ_Define.h203 #define E_XRULE_NUM 7 macro
205 #define E_XRULE_NUM 5 macro
/utopia/UTPA2-700.0.x/modules/pq/hal/curry/pq/include/
H A DdrvPQ_Declare.h165 MS_U8 u8PQ_XRule_IP_Num[E_XRULE_NUM];
166 MS_U8 *pXRule_IP_Index[E_XRULE_NUM];
167 MS_U8 *pXRule_Array[E_XRULE_NUM];
H A DdrvPQ_Define.h197 #define E_XRULE_NUM 7 macro
199 #define E_XRULE_NUM 5 macro
/utopia/UTPA2-700.0.x/modules/pq/hal/kano/pq/include/
H A DdrvPQ_Declare.h165 MS_U8 u8PQ_XRule_IP_Num[E_XRULE_NUM];
166 MS_U8 *pXRule_IP_Index[E_XRULE_NUM];
167 MS_U8 *pXRule_Array[E_XRULE_NUM];
H A DdrvPQ_Define.h201 #define E_XRULE_NUM 7 macro
203 #define E_XRULE_NUM 5 macro
/utopia/UTPA2-700.0.x/modules/pq/hal/mooney/pq/include/
H A DdrvPQ_Declare.h212 MS_U8 u8PQ_XRule_IP_Num[E_XRULE_NUM];
213 MS_U8 *pXRule_IP_Index[E_XRULE_NUM];
214 MS_U8 *pXRule_Array[E_XRULE_NUM];
H A DdrvPQ_Define.h202 #define E_XRULE_NUM 7 macro
204 #define E_XRULE_NUM 5 macro
/utopia/UTPA2-700.0.x/modules/pq/hal/M7621/pq/include/
H A DdrvPQ_Declare.h208 MS_U8 u8PQ_XRule_IP_Num[E_XRULE_NUM];
209 MS_U8 *pXRule_IP_Index[E_XRULE_NUM];
210 MS_U8 *pXRule_Array[E_XRULE_NUM];
H A DdrvPQ_Define.h203 #define E_XRULE_NUM 7 macro
205 #define E_XRULE_NUM 5 macro
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/
H A Dmake34 #define E_XRULE_NUM 5
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmdrv_sc_scaling.c156 #define E_XRULE_NUM 5 macro
H A Dmdrv_sc_scaling.c.0156 #define E_XRULE_NUM 5