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Searched refs:DDC_WRITE_MASK (Results 1 – 17 of 17) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmdrv_hdmi.c3072 DDC_WRITE_MASK(REG_DDC_A_ACCESS,REG_DDC_A_ACCESS_BITS(1),REG_DDC_A_ACCESS_MASK); in MDrv_HDMI_ReadEDID()
3073 … DDC_WRITE_MASK(REG_DDC_A_WRITEADDR,REG_DDC_A_WRITEADDR_BITS(i),REG_DDC_A_WRITEADDR_MASK); in MDrv_HDMI_ReadEDID()
3074 … DDC_WRITE_MASK(REG_DDC_A_READPULSE,REG_DDC_A_READPULSE_BITS(1),REG_DDC_A_READPULSE_MASK); in MDrv_HDMI_ReadEDID()
3080 DDC_WRITE_MASK(REG_DDC_D_ACCESS,REG_DDC_D_ACCESS_BITS(1),REG_DDC_D_ACCESS_MASK); in MDrv_HDMI_ReadEDID()
3081 … DDC_WRITE_MASK(REG_DDC_D_WRITEADDR,REG_DDC_D_WRITEADDR_BITS(i),REG_DDC_D_WRITEADDR_MASK); in MDrv_HDMI_ReadEDID()
3082 … DDC_WRITE_MASK(REG_DDC_D_READPULSE,REG_DDC_D_READPULSE_BITS(1),REG_DDC_D_READPULSE_MASK); in MDrv_HDMI_ReadEDID()
3100 DDC_WRITE_MASK(REG_DDC_A_ACCESS,REG_DDC_A_ACCESS_BITS(0),REG_DDC_A_ACCESS_MASK); in MDrv_HDMI_WriteEDID()
3101 … DDC_WRITE_MASK(REG_DDC_A_WRITEADDR,REG_DDC_A_WRITEADDR_BITS(i),REG_DDC_A_WRITEADDR_MASK); in MDrv_HDMI_WriteEDID()
3102 …DDC_WRITE_MASK(REG_DDC_A_WRITEDATA,REG_DDC_A_WRITEDATA_BITS(*(u8EDID + i)),REG_DDC_A_WRITEDATA_MAS… in MDrv_HDMI_WriteEDID()
3103 … DDC_WRITE_MASK(REG_DDC_A_WRITEPULSE,REG_DDC_A_WRITEPULSE_BITS(1),REG_DDC_A_WRITEPULSE_MASK); in MDrv_HDMI_WriteEDID()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_hdmi.c3065 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
3066 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI0),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
3067 … DDC_WRITE_MASK(REG_DDC_D0_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI0),REG_DDC_D0_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
3070 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
3071 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI1),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
3072 … DDC_WRITE_MASK(REG_DDC_D1_SRAM_BASEADDR,BITS(12:8,DDC_OFFSET_SRAM_DVI1),REG_DDC_D1_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
3075 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
3076 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI2),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
3077 … DDC_WRITE_MASK(REG_DDC_D2_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI2),REG_DDC_D2_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
3080 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_hdmi.c3802 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
3803 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI0),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
3804 … DDC_WRITE_MASK(REG_DDC_D0_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI0),REG_DDC_D0_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
3807 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
3808 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI1),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
3809 … DDC_WRITE_MASK(REG_DDC_D1_SRAM_BASEADDR,BITS(12:8,DDC_OFFSET_SRAM_DVI1),REG_DDC_D1_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
3812 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
3813 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI2),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
3814 … DDC_WRITE_MASK(REG_DDC_D2_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI2),REG_DDC_D2_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
3817 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_hdmi.c5506 DDC_WRITE_MASK(REG_DDC_76_L,BITS(15:15,1),BMASK(15:15));//Kano only in HAL_HDMI_DDCRam_SelectPort()
5511 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5512 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI0),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5513 … DDC_WRITE_MASK(REG_DDC_D0_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI0),REG_DDC_D0_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5516 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5517 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI1),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5518 … DDC_WRITE_MASK(REG_DDC_D1_SRAM_BASEADDR,BITS(12:8,DDC_OFFSET_SRAM_DVI1),REG_DDC_D1_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5521 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5522 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI2),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5523 … DDC_WRITE_MASK(REG_DDC_D2_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI2),REG_DDC_D2_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_hdmi.c5543 DDC_WRITE_MASK(REG_DDC_76_L,BITS(15:15,1),BMASK(15:15));//Kano only in HAL_HDMI_DDCRam_SelectPort()
5548 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5549 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI0),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5550 … DDC_WRITE_MASK(REG_DDC_D0_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI0),REG_DDC_D0_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5553 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5554 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI1),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5555 … DDC_WRITE_MASK(REG_DDC_D1_SRAM_BASEADDR,BITS(12:8,DDC_OFFSET_SRAM_DVI1),REG_DDC_D1_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5558 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5559 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI2),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5560 … DDC_WRITE_MASK(REG_DDC_D2_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI2),REG_DDC_D2_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_hdmi.c5506 DDC_WRITE_MASK(REG_DDC_76_L,BITS(15:15,1),BMASK(15:15));//Kano only in HAL_HDMI_DDCRam_SelectPort()
5511 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5512 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI0),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5513 … DDC_WRITE_MASK(REG_DDC_D0_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI0),REG_DDC_D0_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5516 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5517 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI1),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5518 … DDC_WRITE_MASK(REG_DDC_D1_SRAM_BASEADDR,BITS(12:8,DDC_OFFSET_SRAM_DVI1),REG_DDC_D1_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5521 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5522 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI2),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5523 … DDC_WRITE_MASK(REG_DDC_D2_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI2),REG_DDC_D2_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_hdmi.c5543 DDC_WRITE_MASK(REG_DDC_76_L,BITS(15:15,1),BMASK(15:15));//Kano only in HAL_HDMI_DDCRam_SelectPort()
5548 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5549 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI0),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5550 … DDC_WRITE_MASK(REG_DDC_D0_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI0),REG_DDC_D0_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5553 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5554 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI1),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5555 … DDC_WRITE_MASK(REG_DDC_D1_SRAM_BASEADDR,BITS(12:8,DDC_OFFSET_SRAM_DVI1),REG_DDC_D1_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5558 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5559 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI2),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5560 … DDC_WRITE_MASK(REG_DDC_D2_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI2),REG_DDC_D2_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_hdmi.c5409 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5410 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI0),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5411 … DDC_WRITE_MASK(REG_DDC_D0_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI0),REG_DDC_D0_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5414 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5415 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI1),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5416 … DDC_WRITE_MASK(REG_DDC_D1_SRAM_BASEADDR,BITS(12:8,DDC_OFFSET_SRAM_DVI1),REG_DDC_D1_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5419 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5420 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI2),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5421 … DDC_WRITE_MASK(REG_DDC_D2_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI2),REG_DDC_D2_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5424 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_hdmi.c5524 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5525 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI0),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5526 … DDC_WRITE_MASK(REG_DDC_D0_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI0),REG_DDC_D0_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5529 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5530 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI1),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5531 … DDC_WRITE_MASK(REG_DDC_D1_SRAM_BASEADDR,BITS(12:8,DDC_OFFSET_SRAM_DVI1),REG_DDC_D1_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5534 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5535 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI2),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5536 … DDC_WRITE_MASK(REG_DDC_D2_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI2),REG_DDC_D2_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5539 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_hdmi.c2591 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
2592 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI0),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
2595 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
2596 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI1),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
2599 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
2600 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI2),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
2603 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
2604 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI3),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
2607 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_ADC),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_hdmi.c2591 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
2592 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI0),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
2595 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
2596 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI1),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
2599 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
2600 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI2),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
2603 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
2604 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI3),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
2607 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_ADC),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_hdmi.c6112 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
6113 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI0),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
6114 … DDC_WRITE_MASK(REG_DDC_D0_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI0),REG_DDC_D0_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
6117 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
6118 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI1),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
6119 … DDC_WRITE_MASK(REG_DDC_D1_SRAM_BASEADDR,BITS(12:8,DDC_OFFSET_SRAM_DVI1),REG_DDC_D1_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
6122 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
6123 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI2),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
6124 … DDC_WRITE_MASK(REG_DDC_D2_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI2),REG_DDC_D2_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
6127 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_hdmi.c6115 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
6116 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI0),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
6117 … DDC_WRITE_MASK(REG_DDC_D0_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI0),REG_DDC_D0_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
6120 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
6121 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI1),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
6122 … DDC_WRITE_MASK(REG_DDC_D1_SRAM_BASEADDR,BITS(12:8,DDC_OFFSET_SRAM_DVI1),REG_DDC_D1_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
6125 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
6126 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI2),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
6127 … DDC_WRITE_MASK(REG_DDC_D2_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI2),REG_DDC_D2_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
6130 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_hdmi.c5830 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5831 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI0),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5832 … DDC_WRITE_MASK(REG_DDC_D0_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI0),REG_DDC_D0_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5835 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5836 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI1),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5837 … DDC_WRITE_MASK(REG_DDC_D1_SRAM_BASEADDR,BITS(12:8,DDC_OFFSET_SRAM_DVI1),REG_DDC_D1_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5840 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5841 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI2),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5842 … DDC_WRITE_MASK(REG_DDC_D2_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI2),REG_DDC_D2_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5845 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_hdmi.c6118 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
6119 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI0),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
6120 … DDC_WRITE_MASK(REG_DDC_D0_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI0),REG_DDC_D0_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
6123 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
6124 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI1),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
6125 … DDC_WRITE_MASK(REG_DDC_D1_SRAM_BASEADDR,BITS(12:8,DDC_OFFSET_SRAM_DVI1),REG_DDC_D1_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
6128 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
6129 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI2),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
6130 … DDC_WRITE_MASK(REG_DDC_D2_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI2),REG_DDC_D2_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
6133 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_hdmi.c5830 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5831 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI0),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5832 … DDC_WRITE_MASK(REG_DDC_D0_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI0),REG_DDC_D0_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5835 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5836 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI1),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5837 … DDC_WRITE_MASK(REG_DDC_D1_SRAM_BASEADDR,BITS(12:8,DDC_OFFSET_SRAM_DVI1),REG_DDC_D1_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5840 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
5841 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(12:11,DDC_RAM_SRAM_DVI2),REG_DDC_SRAM_SEL_MASK); in HAL_HDMI_DDCRam_SelectPort()
5842 … DDC_WRITE_MASK(REG_DDC_D2_SRAM_BASEADDR,BITS(4:0,DDC_OFFSET_SRAM_DVI2),REG_DDC_D2_BASEADDR_MASK); in HAL_HDMI_DDCRam_SelectPort()
5845 DDC_WRITE_MASK(REG_DDC_SRAM_SEL,BITS(14:14,DDC_RAM_SRAM_DVI),BMASK(14:14)); in HAL_HDMI_DDCRam_SelectPort()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/
H A Dxc_hwreg_utility2.h713 #define DDC_WRITE_MASK( u32Reg, u16Val, u16Mask)\ macro