| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_pip.c | 515 …MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, !bEnable, CKG_S2_IDCLK2_GATED); // REG_CLKGEN2_65[0], s2_idclk2 in Hal_SC_EnableCLK_for_SUB()
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| H A D | mhal_mux.c | 627 MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, DISABLE, CKG_S2_IDCLK2_GATED); in Hal_SC2_mux_set_mainwin_ip_mux()
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| H A D | mhal_sc.c | 10674 MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, DISABLE, CKG_S2_IDCLK2_GATED); in Hal_SC_Sub_SRAM_PowerDown_Control()
10727 MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, ENABLE, CKG_S2_IDCLK2_GATED); in Hal_SC_Sub_SRAM_PowerDown_Control()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_pip.c | 515 …MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, !bEnable, CKG_S2_IDCLK2_GATED); // REG_CLKGEN2_65[0], s2_idclk2 in Hal_SC_EnableCLK_for_SUB()
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| H A D | mhal_mux.c | 627 MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, DISABLE, CKG_S2_IDCLK2_GATED); in Hal_SC2_mux_set_mainwin_ip_mux()
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| H A D | mhal_sc.c | 10646 MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, DISABLE, CKG_S2_IDCLK2_GATED); in Hal_SC_Sub_SRAM_PowerDown_Control()
10699 MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, ENABLE, CKG_S2_IDCLK2_GATED); in Hal_SC_Sub_SRAM_PowerDown_Control()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | mhal_xc_chip_config.h | 876 #define CKG_S2_IDCLK2_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_pip.c | 540 …MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, !bEnable, CKG_S2_IDCLK2_GATED); // REG_CLKGEN2_65[0], s2_idclk2 in Hal_SC_EnableCLK_for_SUB()
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| H A D | mhal_mux.c | 627 MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, DISABLE, CKG_S2_IDCLK2_GATED); in Hal_SC2_mux_set_mainwin_ip_mux()
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| H A D | mhal_sc.c | 10369 MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, DISABLE, CKG_S2_IDCLK2_GATED); in Hal_SC_Sub_SRAM_PowerDown_Control()
10423 MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, ENABLE, CKG_S2_IDCLK2_GATED); in Hal_SC_Sub_SRAM_PowerDown_Control()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | mhal_xc_chip_config.h | 858 #define CKG_S2_IDCLK2_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_pip.c | 540 …MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, !bEnable, CKG_S2_IDCLK2_GATED); // REG_CLKGEN2_65[0], s2_idclk2 in Hal_SC_EnableCLK_for_SUB()
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| H A D | mhal_mux.c | 627 MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, DISABLE, CKG_S2_IDCLK2_GATED); in Hal_SC2_mux_set_mainwin_ip_mux()
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| H A D | mhal_sc.c | 10397 MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, DISABLE, CKG_S2_IDCLK2_GATED); in Hal_SC_Sub_SRAM_PowerDown_Control()
10451 MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, ENABLE, CKG_S2_IDCLK2_GATED); in Hal_SC_Sub_SRAM_PowerDown_Control()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | mhal_xc_chip_config.h | 922 #define CKG_S2_IDCLK2_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | mhal_xc_chip_config.h | 1037 #define CKG_S2_IDCLK2_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 992 #define CKG_S2_IDCLK2_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | mhal_xc_chip_config.h | 1049 #define CKG_S2_IDCLK2_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 986 #define CKG_S2_IDCLK2_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | mhal_xc_chip_config.h | 1054 #define CKG_S2_IDCLK2_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | mhal_xc_chip_config.h | 1041 #define CKG_S2_IDCLK2_GATED BIT(0) macro
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| /utopia/UTPA2-700.0.x/modules/xc/drv/xc/ |
| H A D | mvideo.c | 560 …MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, ENABLE, CKG_S2_IDCLK2_GATED); // Enable… in MApi_XC_Exit_U2()
1249 …MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, DISABLE, CKG_S2_IDCLK2_GATED); // Enabl… in _MApi_XC_Init_WithoutCreateMutex()
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| H A D | mvideo.c.0 | 557 …MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, ENABLE, CKG_S2_IDCLK2_GATED); // Enable…
1246 …MDrv_WriteRegBit(REG_CKG_S2_IDCLK2, DISABLE, CKG_S2_IDCLK2_GATED); // Enabl…
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