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Searched refs:CKG_S2_FCLK_172MHZ (Results 1 – 9 of 9) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h860 #define CKG_S2_FCLK_172MHZ (0 << 2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h975 #define CKG_S2_FCLK_172MHZ (0 << 2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h930 #define CKG_S2_FCLK_172MHZ (0 << 2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h987 #define CKG_S2_FCLK_172MHZ (0 << 2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h924 #define CKG_S2_FCLK_172MHZ (0 << 2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h992 #define CKG_S2_FCLK_172MHZ (0 << 2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h979 #define CKG_S2_FCLK_172MHZ (0 << 2) macro
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmdrv_sc_scaling.c3729 …PstScalingDownCheck = ((MDrv_ReadByte(REG_CKG_S2_FCLK) & CKG_S2_FCLK_MASK) == CKG_S2_FCLK_172MHZ) ? in MDrv_SC_set_postscaling_ratio()
H A Dmdrv_sc_scaling.c.03713 …PstScalingDownCheck = ((MDrv_ReadByte(REG_CKG_S2_FCLK) & CKG_S2_FCLK_MASK) == CKG_S2_FCLK_172MHZ) ?