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Searched refs:CKG_IDCLK3_GATED (Results 1 – 25 of 38) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_dip.c1142 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Di… in HAL_XC_DIP_Init()
1284 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1444 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Di… in HAL_XC_DIP_ClearIntr()
1554 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
3299 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Di… in HAL_XC_DIP_InterruptDetach()
H A Dmhal_mux.c931 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
937 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_dip.c1143 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Di… in HAL_XC_DIP_Init()
1285 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1445 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Di… in HAL_XC_DIP_ClearIntr()
1555 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
3301 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Di… in HAL_XC_DIP_InterruptDetach()
H A Dmhal_mux.c931 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
937 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_dip.c1412 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Dis… in HAL_XC_DIP_Init()
1550 MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); in HAL_XC_DIP_EnableCaptureStream()
1739 …MDrv_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Disabl… in HAL_XC_DIP_ClearIntr()
1837 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
4248 …MDrv_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Disabl… in HAL_XC_DIP_InterruptDetach()
H A Dmhal_mux.c714 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
720 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_mux.c728 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
734 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_mux.c723 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
729 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_mux.c714 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
720 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_mux.c852 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
858 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_mux.c931 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
937 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_mux.c931 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
937 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_mux.c919 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
925 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_mux.c929 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
935 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_xc_chip_config.h590 #define CKG_IDCLK3_GATED BIT(4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_xc_chip_config.h590 #define CKG_IDCLK3_GATED BIT(4) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h789 #define CKG_IDCLK3_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h795 #define CKG_IDCLK3_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h788 #define CKG_IDCLK3_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h782 #define CKG_IDCLK3_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h739 #define CKG_IDCLK3_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h843 #define CKG_IDCLK3_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h803 #define CKG_IDCLK3_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h855 #define CKG_IDCLK3_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h793 #define CKG_IDCLK3_GATED BIT(0) macro

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