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Searched refs:CKG_FCLK_CLK_ODCLK (Results 1 – 18 of 18) sorted by relevance

/utopia/UTPA2-700.0.x/modules/pws/hal/maldives/pws/
H A DregCLKGEN.h339 #define CKG_FCLK_CLK_ODCLK (2 << 2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/k6/pws/
H A DregCLKGEN.h339 #define CKG_FCLK_CLK_ODCLK (2 << 2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/macan/pws/
H A DregCLKGEN.h339 #define CKG_FCLK_CLK_ODCLK (2UL << 2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/mooney/pws/
H A DregCLKGEN.h339 #define CKG_FCLK_CLK_ODCLK (2UL << 2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/messi/pws/
H A DregCLKGEN.h339 #define CKG_FCLK_CLK_ODCLK (2UL << 2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/manhattan/pws/
H A DregCLKGEN.h339 #define CKG_FCLK_CLK_ODCLK (2UL << 2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/k6lite/pws/
H A DregCLKGEN.h339 #define CKG_FCLK_CLK_ODCLK (2 << 2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/M7821/pws/
H A DregCLKGEN.h339 #define CKG_FCLK_CLK_ODCLK (2UL << 2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/mainz/pws/
H A DregCLKGEN.h339 #define CKG_FCLK_CLK_ODCLK (2UL << 2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/mustang/pws/
H A DregCLKGEN.h339 #define CKG_FCLK_CLK_ODCLK (2 << 2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/maxim/pws/
H A DregCLKGEN.h339 #define CKG_FCLK_CLK_ODCLK (2UL << 2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/M7621/pws/
H A DregCLKGEN.h339 #define CKG_FCLK_CLK_ODCLK (2UL << 2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/curry/pws/
H A DregCLKGEN.h339 #define CKG_FCLK_CLK_ODCLK (2 << 2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/kano/pws/
H A DregCLKGEN.h339 #define CKG_FCLK_CLK_ODCLK (2 << 2) macro
/utopia/UTPA2-700.0.x/modules/pws/hal/maserati/pws/
H A DregCLKGEN.h339 #define CKG_FCLK_CLK_ODCLK (2UL << 2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_xc_chip_config.h515 #define CKG_FCLK_CLK_ODCLK (2 << 2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_xc_chip_config.h515 #define CKG_FCLK_CLK_ODCLK (2 << 2) macro
/utopia/UTPA2-700.0.x/modules/ve/drv/ve/include/
H A Dve_Analog_Reg.h1404 #define CKG_FCLK_CLK_ODCLK (2 << 2) macro