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Searched refs:BYTES_IN_MIU_LINE (Results 1 – 25 of 81) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/audio/hal/kano/audio/
H A Daudio_comm2.h185 #define DSP2_PM_PREFETCH_DDRADDR DSP2_PM_PREFETCH_DSPADDR*3/BYTES_IN_MIU_LINE
187 #define DSP2_PM_PREFETCH2_DDRADDR DSP2_PM_PREFETCH2_DSPADDR*3/BYTES_IN_MIU_LINE
650 .const DSP2_TO_COMMON_DRAM_OFFSET = (ASND_DSP_DDR_SIZE / BYTES_IN_MIU_LINE);
653 … .const DSP2_SPDIF_DLY_DRAM_BASE = (OFFSET_SPDIF_DLY_DRAM_BASE / BYTES_IN_MIU_LINE);
654 … .const DSP2_SPDIF_DLY_DRAM_SIZE = ((SPDIF_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1);
657 .const HDMI_DLY_DRAM_BASE = (SE_HDMI_DLY_DRAM_BASE / BYTES_IN_MIU_LINE);
658 … .const HDMI_DLY_DRAM_SIZE = (SE_HDMI_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1;
661 … .const DSP2_DMA_START_DRAM_BASE1 = (OFFSET_SE_MAIN_IN_DRAM_ADDR / BYTES_IN_MIU_LINE);
662 .const DSP2_DMA_START_DRAM_SIZE1 = (SE_MAIN_IN_DRAM_SIZE / BYTES_IN_MIU_LINE);
663 … .const DSP2_DMA_START_DRAM_BASE2 = (OFFSET_SE_MAIN_OUT_DRAM_ADDR / BYTES_IN_MIU_LINE);
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/utopia/UTPA2-700.0.x/modules/audio/hal/k6lite/audio/
H A Daudio_comm2.h197 #define DSP2_PM_PREFETCH_DDRADDR DSP2_PM_PREFETCH_DSPADDR*3/BYTES_IN_MIU_LINE
199 #define DSP2_PM_PREFETCH2_DDRADDR DSP2_PM_PREFETCH2_DSPADDR*3/BYTES_IN_MIU_LINE
691 .const DSP2_TO_COMMON_DRAM_OFFSET = (ASND_DSP_DDR_SIZE / BYTES_IN_MIU_LINE);
694 … .const DSP2_SPDIF_DLY_DRAM_BASE = (OFFSET_SPDIF_DLY_DRAM_BASE / BYTES_IN_MIU_LINE);
695 … .const DSP2_SPDIF_DLY_DRAM_SIZE = ((SPDIF_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1);
698 .const HDMI_DLY_DRAM_BASE = (SE_HDMI_DLY_DRAM_BASE / BYTES_IN_MIU_LINE);
699 … .const HDMI_DLY_DRAM_SIZE = (SE_HDMI_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1;
702 … .const DSP2_DMA_START_DRAM_BASE1 = (OFFSET_SE_MAIN_IN_DRAM_ADDR / BYTES_IN_MIU_LINE);
703 .const DSP2_DMA_START_DRAM_SIZE1 = (SE_MAIN_IN_DRAM_SIZE / BYTES_IN_MIU_LINE);
704 … .const DSP2_DMA_START_DRAM_BASE2 = (OFFSET_SE_MAIN_OUT_DRAM_ADDR / BYTES_IN_MIU_LINE);
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H A DhalAUDIO.c213 #define HW_DMA_RDR1_BUF_ADDR (DSP2_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
214 #define HW_DMA_RDR1_BUF_SIZE ((DSP2_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
218 #define HW_DMA_RDR2_BUF_ADDR (DSP2_HW_DMA_READER2_DRAM_BASE * BYTES_IN_MIU_LINE)
219 #define HW_DMA_RDR2_BUF_SIZE ((DSP2_HW_DMA_READER2_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
223 #define SW_DMA_RDR1_BUF_ADDR (DSP2_SW_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
224 #define SW_DMA_RDR1_BUF_SIZE ((DSP2_SW_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
239 #define PCM_CAPTURE1_BUF_ADDR (DSP2_PCM_CAPTURE_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
240 #define PCM_CAPTURE1_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
245 #define PCM_CAPTURE2_BUF_ADDR (DSP2_PCM_CAPTURE2_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
246 #define PCM_CAPTURE2_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
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/utopia/UTPA2-700.0.x/modules/audio/hal/k6/audio/
H A Daudio_comm2.h173 #define DSP2_PM_PREFETCH_DDRADDR DSP2_PM_PREFETCH_DSPADDR*3/BYTES_IN_MIU_LINE
175 #define DSP2_PM_PREFETCH2_DDRADDR DSP2_PM_PREFETCH2_DSPADDR*3/BYTES_IN_MIU_LINE
625 .const DSP2_TO_COMMON_DRAM_OFFSET = ASND_DSP_DDR_SIZE / BYTES_IN_MIU_LINE;
628 … .const DSP2_SPDIF_DLY_DRAM_BASE = (OFFSET_SPDIF_DLY_DRAM_BASE / BYTES_IN_MIU_LINE);
629 … .const DSP2_SPDIF_DLY_DRAM_SIZE = ((SPDIF_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1);
632 .const HDMI_DLY_DRAM_BASE = SE_HDMI_DLY_DRAM_BASE / BYTES_IN_MIU_LINE;
633 … .const HDMI_DLY_DRAM_SIZE = (SE_HDMI_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1;
636 .const DSP2_DMA_START_DRAM_BASE1 = OFFSET_SE_MAIN_IN_DRAM_ADDR / BYTES_IN_MIU_LINE;
637 .const DSP2_DMA_START_DRAM_SIZE1 = SE_MAIN_IN_DRAM_SIZE / BYTES_IN_MIU_LINE;
638 .const DSP2_DMA_START_DRAM_BASE2 = OFFSET_SE_MAIN_OUT_DRAM_ADDR / BYTES_IN_MIU_LINE;
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H A DhalAUDIO.c212 #define HW_DMA_RDR1_BUF_ADDR (DSP2_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
213 #define HW_DMA_RDR1_BUF_SIZE ((DSP2_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
217 #define HW_DMA_RDR2_BUF_ADDR (DSP2_HW_DMA_READER2_DRAM_BASE * BYTES_IN_MIU_LINE)
218 #define HW_DMA_RDR2_BUF_SIZE ((DSP2_HW_DMA_READER2_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
222 #define SW_DMA_RDR1_BUF_ADDR (DSP2_SW_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
223 #define SW_DMA_RDR1_BUF_SIZE ((DSP2_SW_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
238 #define PCM_CAPTURE1_BUF_ADDR (DSP2_PCM_CAPTURE_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
239 #define PCM_CAPTURE1_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
244 #define PCM_CAPTURE2_BUF_ADDR (DSP2_PCM_CAPTURE2_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
245 #define PCM_CAPTURE2_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
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/utopia/UTPA2-700.0.x/modules/audio/hal/M7821/audio/
H A Daudio_comm2.h189 #define DSP2_PM_PREFETCH3_DDRADDR (DSP2_PM_PREFETCH3_DSPADDR*3/BYTES_IN_MIU_LINE)
191 #define DSP2_PM_PREFETCH_DDRADDR (DSP2_PM_PREFETCH_DSPADDR*3/BYTES_IN_MIU_LINE)
193 #define DSP2_PM_PREFETCH2_DDRADDR (DSP2_PM_PREFETCH2_DSPADDR*3/BYTES_IN_MIU_LINE)
195 #define DSP2_PM_PREFETCH4_DDRADDR (DSP2_PM_PREFETCH4_DSPADDR*3/BYTES_IN_MIU_LINE)
289 #define MIU_OFFSET_SE_Coeff_48k (DSP2fetch3Addr_48kAddr*3/BYTES_IN_MIU_LINE )
290 #define MIU_OFFSET_SE_Coeff_96k (DSP2fetch3Addr_96kAddr*3/BYTES_IN_MIU_LINE )
291 #define MIU_OFFSET_SE_Coeff_192k (DSP2fetch3Addr_192kAddr*3/BYTES_IN_MIU_LINE)
292 #define DMA_SIZE_SE_Coeff (144*3/BYTES_IN_MIU_LINE )
785 …SS_FETCH_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_FETCH_CHANNELS*3/BYTES_IN_MIU_LINE)
786 …SS_STORE_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_STORE_CHANNELS*3/BYTES_IN_MIU_LINE)
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H A DhalAUDIO.c171 #define HW_DMA_RDR1_BUF_ADDR (DSP2_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
172 #define HW_DMA_RDR1_BUF_SIZE ((DSP2_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
176 #define HW_DMA_RDR2_BUF_ADDR (DSP2_HW_DMA_READER2_DRAM_BASE * BYTES_IN_MIU_LINE)
177 #define HW_DMA_RDR2_BUF_SIZE ((DSP2_HW_DMA_READER2_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
181 #define SW_DMA_RDR1_BUF_ADDR (DSP2_SW_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
182 #define SW_DMA_RDR1_BUF_SIZE ((DSP2_SW_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
197 #define PCM_CAPTURE1_BUF_ADDR (DSP2_PCM_CAPTURE_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
198 #define PCM_CAPTURE1_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
203 #define PCM_CAPTURE2_BUF_ADDR (DSP2_PCM_CAPTURE2_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
204 #define PCM_CAPTURE2_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
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/utopia/UTPA2-700.0.x/modules/audio/hal/maxim/audio/
H A Daudio_comm2.h207 #define DSP2_PM_PREFETCH3_DDRADDR (DSP2_PM_PREFETCH3_DSPADDR*3/BYTES_IN_MIU_LINE)
209 #define DSP2_PM_PREFETCH_DDRADDR (DSP2_PM_PREFETCH_DSPADDR*3/BYTES_IN_MIU_LINE)
211 #define DSP2_PM_PREFETCH2_DDRADDR (DSP2_PM_PREFETCH2_DSPADDR*3/BYTES_IN_MIU_LINE)
213 #define DSP2_PM_PREFETCH4_DDRADDR (DSP2_PM_PREFETCH4_DSPADDR*3/BYTES_IN_MIU_LINE)
840 …SS_FETCH_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_FETCH_CHANNELS*3/BYTES_IN_MIU_LINE)
841 …SS_STORE_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_STORE_CHANNELS*3/BYTES_IN_MIU_LINE)
848 .const DSP2_TO_COMMON_DRAM_OFFSET = (ASND_DSP_DDR_SIZE / BYTES_IN_MIU_LINE);
851 … .const DSP2_SPDIF_DLY_DRAM_BASE = (OFFSET_SPDIF_DLY_DRAM_BASE / BYTES_IN_MIU_LINE);
852 … .const DSP2_SPDIF_DLY_DRAM_SIZE = ((SPDIF_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1);
855 … .const DSP2_DMA_START_DRAM_BASE1 = (OFFSET_SE_MAIN_IN_DRAM_ADDR / BYTES_IN_MIU_LINE);
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H A DhalAUDIO.c210 #define HW_DMA_RDR1_BUF_ADDR (DSP2_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
211 #define HW_DMA_RDR1_BUF_SIZE ((DSP2_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
215 #define HW_DMA_RDR2_BUF_ADDR (DSP2_HW_DMA_READER2_DRAM_BASE * BYTES_IN_MIU_LINE)
216 #define HW_DMA_RDR2_BUF_SIZE ((DSP2_HW_DMA_READER2_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
220 #define SW_DMA_RDR1_BUF_ADDR (DSP2_SW_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
221 #define SW_DMA_RDR1_BUF_SIZE ((DSP2_SW_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
236 #define PCM_CAPTURE1_BUF_ADDR (DSP2_PCM_CAPTURE_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
237 #define PCM_CAPTURE1_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
242 #define PCM_CAPTURE2_BUF_ADDR (DSP2_PCM_CAPTURE2_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
243 #define PCM_CAPTURE2_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
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/utopia/UTPA2-700.0.x/modules/audio/hal/maserati/audio/
H A Daudio_comm2.h195 #define DSP2_PM_PREFETCH3_DDRADDR (DSP2_PM_PREFETCH3_DSPADDR*3/BYTES_IN_MIU_LINE)
197 #define DSP2_PM_PREFETCH_DDRADDR (DSP2_PM_PREFETCH_DSPADDR*3/BYTES_IN_MIU_LINE)
199 #define DSP2_PM_PREFETCH2_DDRADDR (DSP2_PM_PREFETCH2_DSPADDR*3/BYTES_IN_MIU_LINE)
201 #define DSP2_PM_PREFETCH4_DDRADDR (DSP2_PM_PREFETCH4_DSPADDR*3/BYTES_IN_MIU_LINE)
295 #define MIU_OFFSET_SE_Coeff_48k (DSP2fetch3Addr_48kAddr*3/BYTES_IN_MIU_LINE )
296 #define MIU_OFFSET_SE_Coeff_96k (DSP2fetch3Addr_96kAddr*3/BYTES_IN_MIU_LINE )
297 #define MIU_OFFSET_SE_Coeff_192k (DSP2fetch3Addr_192kAddr*3/BYTES_IN_MIU_LINE)
298 #define DMA_SIZE_SE_Coeff (144*3/BYTES_IN_MIU_LINE )
819 …SS_FETCH_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_FETCH_CHANNELS*3/BYTES_IN_MIU_LINE)
820 …SS_STORE_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_STORE_CHANNELS*3/BYTES_IN_MIU_LINE)
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H A DhalAUDIO.c171 #define HW_DMA_RDR1_BUF_ADDR (DSP2_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
172 #define HW_DMA_RDR1_BUF_SIZE ((DSP2_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
176 #define HW_DMA_RDR2_BUF_ADDR (DSP2_HW_DMA_READER2_DRAM_BASE * BYTES_IN_MIU_LINE)
177 #define HW_DMA_RDR2_BUF_SIZE ((DSP2_HW_DMA_READER2_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
181 #define SW_DMA_RDR1_BUF_ADDR (DSP2_SW_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
182 #define SW_DMA_RDR1_BUF_SIZE ((DSP2_SW_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
197 #define PCM_CAPTURE1_BUF_ADDR (DSP2_PCM_CAPTURE_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
198 #define PCM_CAPTURE1_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
203 #define PCM_CAPTURE2_BUF_ADDR (DSP2_PCM_CAPTURE2_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
204 #define PCM_CAPTURE2_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
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/utopia/UTPA2-700.0.x/modules/audio/hal/M7621/audio/
H A Daudio_comm2.h189 #define DSP2_PM_PREFETCH3_DDRADDR (DSP2_PM_PREFETCH3_DSPADDR*3/BYTES_IN_MIU_LINE)
191 #define DSP2_PM_PREFETCH_DDRADDR (DSP2_PM_PREFETCH_DSPADDR*3/BYTES_IN_MIU_LINE)
193 #define DSP2_PM_PREFETCH2_DDRADDR (DSP2_PM_PREFETCH2_DSPADDR*3/BYTES_IN_MIU_LINE)
195 #define DSP2_PM_PREFETCH4_DDRADDR (DSP2_PM_PREFETCH4_DSPADDR*3/BYTES_IN_MIU_LINE)
801 …SS_FETCH_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_FETCH_CHANNELS*3/BYTES_IN_MIU_LINE)
802 …SS_STORE_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_STORE_CHANNELS*3/BYTES_IN_MIU_LINE)
809 .const DSP2_TO_COMMON_DRAM_OFFSET = (ASND_DSP_DDR_SIZE / BYTES_IN_MIU_LINE);
812 … .const DSP2_SPDIF_DLY_DRAM_BASE = (OFFSET_SPDIF_DLY_DRAM_BASE / BYTES_IN_MIU_LINE);
813 … .const DSP2_SPDIF_DLY_DRAM_SIZE = ((SPDIF_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1);
816 … .const DSP2_DMA_START_DRAM_BASE1 = (OFFSET_SE_MAIN_IN_DRAM_ADDR / BYTES_IN_MIU_LINE);
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H A DhalAUDIO.c210 #define HW_DMA_RDR1_BUF_ADDR (DSP2_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
211 #define HW_DMA_RDR1_BUF_SIZE ((DSP2_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
215 #define HW_DMA_RDR2_BUF_ADDR (DSP2_HW_DMA_READER2_DRAM_BASE * BYTES_IN_MIU_LINE)
216 #define HW_DMA_RDR2_BUF_SIZE ((DSP2_HW_DMA_READER2_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
220 #define SW_DMA_RDR1_BUF_ADDR (DSP2_SW_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
221 #define SW_DMA_RDR1_BUF_SIZE ((DSP2_SW_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
236 #define PCM_CAPTURE1_BUF_ADDR (DSP2_PCM_CAPTURE_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
237 #define PCM_CAPTURE1_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
242 #define PCM_CAPTURE2_BUF_ADDR (DSP2_PCM_CAPTURE2_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
243 #define PCM_CAPTURE2_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
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/utopia/UTPA2-700.0.x/modules/audio/hal/macan/audio/
H A Daudio_comm2.h195 #define DSP2_PM_PREFETCH3_DDRADDR (DSP2_PM_PREFETCH3_DSPADDR*3/BYTES_IN_MIU_LINE)
197 #define DSP2_PM_PREFETCH_DDRADDR (DSP2_PM_PREFETCH_DSPADDR*3/BYTES_IN_MIU_LINE)
199 #define DSP2_PM_PREFETCH2_DDRADDR (DSP2_PM_PREFETCH2_DSPADDR*3/BYTES_IN_MIU_LINE)
201 #define DSP2_PM_PREFETCH4_DDRADDR (DSP2_PM_PREFETCH4_DSPADDR*3/BYTES_IN_MIU_LINE)
810 …SS_FETCH_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_FETCH_CHANNELS*3/BYTES_IN_MIU_LINE)
811 …SS_STORE_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_STORE_CHANNELS*3/BYTES_IN_MIU_LINE)
818 .const DSP2_TO_COMMON_DRAM_OFFSET = (ASND_DSP_DDR_SIZE / BYTES_IN_MIU_LINE);
821 … .const DSP2_SPDIF_DLY_DRAM_BASE = (OFFSET_SPDIF_DLY_DRAM_BASE / BYTES_IN_MIU_LINE);
822 … .const DSP2_SPDIF_DLY_DRAM_SIZE = ((SPDIF_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1);
825 … .const DSP2_DMA_START_DRAM_BASE1 = (OFFSET_SE_MAIN_IN_DRAM_ADDR / BYTES_IN_MIU_LINE);
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/utopia/UTPA2-700.0.x/modules/audio/hal/mustang/audio/
H A Daudio_comm2.h195 #define DSP2_PM_PREFETCH3_DDRADDR (DSP2_PM_PREFETCH3_DSPADDR*3/BYTES_IN_MIU_LINE)
197 #define DSP2_PM_PREFETCH_DDRADDR (DSP2_PM_PREFETCH_DSPADDR*3/BYTES_IN_MIU_LINE)
199 #define DSP2_PM_PREFETCH2_DDRADDR (DSP2_PM_PREFETCH2_DSPADDR*3/BYTES_IN_MIU_LINE)
201 #define DSP2_PM_PREFETCH4_DDRADDR (DSP2_PM_PREFETCH4_DSPADDR*3/BYTES_IN_MIU_LINE)
807 …SS_FETCH_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_FETCH_CHANNELS*3/BYTES_IN_MIU_LINE)
808 …SS_STORE_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_STORE_CHANNELS*3/BYTES_IN_MIU_LINE)
815 .const DSP2_TO_COMMON_DRAM_OFFSET = (ASND_DSP_DDR_SIZE / BYTES_IN_MIU_LINE);
818 … .const DSP2_SPDIF_DLY_DRAM_BASE = (OFFSET_SPDIF_DLY_DRAM_BASE / BYTES_IN_MIU_LINE);
819 … .const DSP2_SPDIF_DLY_DRAM_SIZE = ((SPDIF_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1);
822 … .const DSP2_DMA_START_DRAM_BASE1 = (OFFSET_SE_MAIN_IN_DRAM_ADDR / BYTES_IN_MIU_LINE);
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/utopia/UTPA2-700.0.x/modules/audio/hal/curry/audio/
H A Daudio_comm2.h168 #define DSP2_PM_PREFETCH_DDRADDR DSP2_PM_PREFETCH_DSPADDR*3/BYTES_IN_MIU_LINE
170 #define DSP2_PM_PREFETCH2_DDRADDR DSP2_PM_PREFETCH2_DSPADDR*3/BYTES_IN_MIU_LINE
645 .const DSP2_TO_COMMON_DRAM_OFFSET = ASND_DSP_DDR_SIZE / BYTES_IN_MIU_LINE;
648 … .const DSP2_SPDIF_DLY_DRAM_BASE = (OFFSET_SPDIF_DLY_DRAM_BASE / BYTES_IN_MIU_LINE);
649 … .const DSP2_SPDIF_DLY_DRAM_SIZE = ((SPDIF_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1);
655 .const DSP2_DMA_START_DRAM_BASE1 = OFFSET_SE_MAIN_IN_DRAM_ADDR / BYTES_IN_MIU_LINE;
656 .const DSP2_DMA_START_DRAM_SIZE1 = SE_MAIN_IN_DRAM_SIZE / BYTES_IN_MIU_LINE;
657 .const DSP2_DMA_START_DRAM_BASE2 = OFFSET_SE_MAIN_OUT_DRAM_ADDR / BYTES_IN_MIU_LINE;
658 .const DSP2_DMA_START_DRAM_SIZE2 = SE_MAIN_OUT_DRAM_SIZE / BYTES_IN_MIU_LINE;
681 … .const DSP2_SPDIF_DRAM_BASE = OFFSET_SPDIF_NONPCM_DRAM_BASE / BYTES_IN_MIU_LINE;
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H A DhalAUDIO.c210 #define HW_DMA_RDR1_BUF_ADDR (DSP2_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
211 #define HW_DMA_RDR1_BUF_SIZE ((DSP2_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
215 #define HW_DMA_RDR2_BUF_ADDR (DSP2_HW_DMA_READER2_DRAM_BASE * BYTES_IN_MIU_LINE)
216 #define HW_DMA_RDR2_BUF_SIZE ((DSP2_HW_DMA_READER2_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
220 #define SW_DMA_RDR1_BUF_ADDR (DSP2_SW_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
221 #define SW_DMA_RDR1_BUF_SIZE ((DSP2_SW_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
236 #define PCM_CAPTURE1_BUF_ADDR (DSP2_PCM_CAPTURE_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
237 #define PCM_CAPTURE1_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
242 #define PCM_CAPTURE2_BUF_ADDR (DSP2_PCM_CAPTURE2_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
243 #define PCM_CAPTURE2_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
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/utopia/UTPA2-700.0.x/modules/audio/hal/mooney/audio/
H A Daudio_comm2.h172 #define DSP2_PM_PREFETCH_DDRADDR DSP2_PM_PREFETCH_DSPADDR*3/BYTES_IN_MIU_LINE
174 #define DSP2_PM_PREFETCH2_DDRADDR DSP2_PM_PREFETCH2_DSPADDR*3/BYTES_IN_MIU_LINE
738 …SS_FETCH_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_FETCH_CHANNELS*3/BYTES_IN_MIU_LINE)
739 …SS_STORE_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_STORE_CHANNELS*3/BYTES_IN_MIU_LINE)
746 .const DSP2_TO_COMMON_DRAM_OFFSET = ASND_DSP_DDR_SIZE / BYTES_IN_MIU_LINE;
749 … .const DSP2_SPDIF_DLY_DRAM_BASE = OFFSET_SPDIF_DLY_DRAM_BASE / BYTES_IN_MIU_LINE;
750 … .const DSP2_SPDIF_DLY_DRAM_SIZE = (SPDIF_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1;
753 … .const DSP2_DMA_START_DRAM_BASE1 = OFFSET_SE_MAIN_IN_DRAM_ADDR / BYTES_IN_MIU_LINE;
754 .const DSP2_DMA_START_DRAM_SIZE1 = SE_MAIN_IN_DRAM_SIZE / BYTES_IN_MIU_LINE;
755 … .const DSP2_DMA_START_DRAM_BASE2 = OFFSET_SE_MAIN_OUT_DRAM_ADDR / BYTES_IN_MIU_LINE;
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H A DhalAUDIO.c206 #define HW_DMA_RDR1_BUF_ADDR (DSP2_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
207 #define HW_DMA_RDR1_BUF_SIZE ((DSP2_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
211 #define HW_DMA_RDR2_BUF_ADDR (DSP2_HW_DMA_READER2_DRAM_BASE * BYTES_IN_MIU_LINE)
212 #define HW_DMA_RDR2_BUF_SIZE ((DSP2_HW_DMA_READER2_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
216 #define SW_DMA_RDR1_BUF_ADDR (DSP2_SW_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
217 #define SW_DMA_RDR1_BUF_SIZE ((DSP2_SW_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
232 #define PCM_CAPTURE1_BUF_ADDR (DSP2_PCM_CAPTURE_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
233 #define PCM_CAPTURE1_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
238 #define PCM_CAPTURE2_BUF_ADDR (DSP2_PCM_CAPTURE2_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
239 #define PCM_CAPTURE2_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
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/utopia/UTPA2-700.0.x/modules/audio/hal/maldives/audio/
H A Daudio_comm2.h172 #define DSP2_PM_PREFETCH_DDRADDR DSP2_PM_PREFETCH_DSPADDR*3/BYTES_IN_MIU_LINE
174 #define DSP2_PM_PREFETCH2_DDRADDR DSP2_PM_PREFETCH2_DSPADDR*3/BYTES_IN_MIU_LINE
738 …SS_FETCH_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_FETCH_CHANNELS*3/BYTES_IN_MIU_LINE)
739 …SS_STORE_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_STORE_CHANNELS*3/BYTES_IN_MIU_LINE)
746 .const DSP2_TO_COMMON_DRAM_OFFSET = ASND_DSP_DDR_SIZE / BYTES_IN_MIU_LINE;
749 … .const DSP2_SPDIF_DLY_DRAM_BASE = OFFSET_SPDIF_DLY_DRAM_BASE / BYTES_IN_MIU_LINE;
750 … .const DSP2_SPDIF_DLY_DRAM_SIZE = (SPDIF_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1;
753 … .const DSP2_DMA_START_DRAM_BASE1 = OFFSET_SE_MAIN_IN_DRAM_ADDR / BYTES_IN_MIU_LINE;
754 .const DSP2_DMA_START_DRAM_SIZE1 = SE_MAIN_IN_DRAM_SIZE / BYTES_IN_MIU_LINE;
755 … .const DSP2_DMA_START_DRAM_BASE2 = OFFSET_SE_MAIN_OUT_DRAM_ADDR / BYTES_IN_MIU_LINE;
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/utopia/UTPA2-700.0.x/modules/audio/hal/manhattan/audio/
H A Daudio_comm2.h169 #define DSP2_PM_PREFETCH_DDRADDR DSP2_PM_PREFETCH_DSPADDR*3/BYTES_IN_MIU_LINE
171 #define DSP2_PM_PREFETCH2_DDRADDR DSP2_PM_PREFETCH2_DSPADDR*3/BYTES_IN_MIU_LINE
692 …SS_FETCH_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_FETCH_CHANNELS*3/BYTES_IN_MIU_LINE)
693 …SS_STORE_FRAME_LINE_SIZE (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_STORE_CHANNELS*3/BYTES_IN_MIU_LINE)
700 .const DSP2_TO_COMMON_DRAM_OFFSET = ASND_DSP_DDR_SIZE / BYTES_IN_MIU_LINE;
703 … .const DSP2_SPDIF_DLY_DRAM_BASE = OFFSET_SPDIF_DLY_DRAM_BASE / BYTES_IN_MIU_LINE;
704 … .const DSP2_SPDIF_DLY_DRAM_SIZE = (SPDIF_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1;
707 … .const DSP2_DMA_START_DRAM_BASE1 = OFFSET_SE_MAIN_IN_DRAM_ADDR / BYTES_IN_MIU_LINE;
708 .const DSP2_DMA_START_DRAM_SIZE1 = SE_MAIN_IN_DRAM_SIZE / BYTES_IN_MIU_LINE;
709 … .const DSP2_DMA_START_DRAM_BASE2 = OFFSET_SE_MAIN_OUT_DRAM_ADDR / BYTES_IN_MIU_LINE;
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/utopia/UTPA2-700.0.x/modules/audio/hal/mainz/audio/
H A Daudio_comm2.h155 #define DSP_TO_COMMON_DRAM_OFFSET (DSP_DDR_SIZE / BYTES_IN_MIU_LINE)
158 … #define DSP2_SPDIF_DLY_DRAM_BASE (OFFSET_SPDIF_DLY_DRAM_BASE / BYTES_IN_MIU_LINE)
159 … #define DSP2_SPDIF_DLY_DRAM_SIZE ((SPDIF_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1)
162 …M_BASEADDR (OFFSET_MSTAR_SURROUND_DRAM_ADDR / BYTES_IN_MIU_LINE) …
163 … ((OFFSET_MSTAR_SURROUND_DRAM_ADDR + MSTAR_SURROUND_DRAM_SIZE) / BYTES_IN_MIU_LINE) // Line Ad…
166 …RAM_KTV_BASEADDR (OFFSET_KTV_SURROUND_DRAM_ADDR / BYTES_IN_MIU_LINE) …
167 … ((OFFSET_KTV_SURROUND_DRAM_ADDR + KTV_SURROUND_DRAM_SIZE) / BYTES_IN_MIU_LINE) // Line ad…
170 #define DSP2_ES1_DRAM_BASE (OFFSET_ES1_DRAM_ADDR / BYTES_IN_MIU_LINE)
171 …#define DSP2_ES1_DRAM_SIZE ((ES1_DRAM_SIZE_BYTE / BYTES_IN_MIU_LINE) - 1) …
175 … #define DSP2_DM_PREFETCH_DRAM_BASE (OFFSET_DM_PREFETCH_DRAM_ADDR / BYTES_IN_MIU_LINE)
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H A DhalAUDIO.c169 #define HW_DMA_RDR1_BUF_ADDR (DSP2_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
170 #define HW_DMA_RDR1_BUF_SIZE ((DSP2_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
174 #define HW_DMA_RDR2_BUF_ADDR (DSP2_HW_DMA_READER2_DRAM_BASE * BYTES_IN_MIU_LINE)
175 #define HW_DMA_RDR2_BUF_SIZE ((DSP2_HW_DMA_READER2_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
179 #define SW_DMA_RDR1_BUF_ADDR (DSP2_SW_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
180 #define SW_DMA_RDR1_BUF_SIZE ((DSP2_SW_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
195 #define PCM_CAPTURE1_BUF_ADDR (DSP2_PCM_CAPTURE_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
196 #define PCM_CAPTURE1_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
201 #define PCM_CAPTURE2_BUF_ADDR (DSP2_PCM_CAPTURE2_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
202 #define PCM_CAPTURE2_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
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/utopia/UTPA2-700.0.x/modules/audio/hal/messi/audio/
H A Daudio_comm2.h155 #define DSP_TO_COMMON_DRAM_OFFSET (DSP_DDR_SIZE / BYTES_IN_MIU_LINE)
158 … #define DSP2_SPDIF_DLY_DRAM_BASE (OFFSET_SPDIF_DLY_DRAM_BASE / BYTES_IN_MIU_LINE)
159 … #define DSP2_SPDIF_DLY_DRAM_SIZE ((SPDIF_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1)
162 …M_BASEADDR (OFFSET_MSTAR_SURROUND_DRAM_ADDR / BYTES_IN_MIU_LINE) …
163 … ((OFFSET_MSTAR_SURROUND_DRAM_ADDR + MSTAR_SURROUND_DRAM_SIZE) / BYTES_IN_MIU_LINE) // Line Ad…
166 …RAM_KTV_BASEADDR (OFFSET_KTV_SURROUND_DRAM_ADDR / BYTES_IN_MIU_LINE) …
167 … ((OFFSET_KTV_SURROUND_DRAM_ADDR + KTV_SURROUND_DRAM_SIZE) / BYTES_IN_MIU_LINE) // Line ad…
170 #define DSP2_ES1_DRAM_BASE (OFFSET_ES1_DRAM_ADDR / BYTES_IN_MIU_LINE)
171 …#define DSP2_ES1_DRAM_SIZE ((ES1_DRAM_SIZE_BYTE / BYTES_IN_MIU_LINE) - 1) …
175 … #define DSP2_DM_PREFETCH_DRAM_BASE (OFFSET_DM_PREFETCH_DRAM_ADDR / BYTES_IN_MIU_LINE)
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H A DhalAUDIO.c169 #define HW_DMA_RDR1_BUF_ADDR (DSP2_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
170 #define HW_DMA_RDR1_BUF_SIZE ((DSP2_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
174 #define HW_DMA_RDR2_BUF_ADDR (DSP2_HW_DMA_READER2_DRAM_BASE * BYTES_IN_MIU_LINE)
175 #define HW_DMA_RDR2_BUF_SIZE ((DSP2_HW_DMA_READER2_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
179 #define SW_DMA_RDR1_BUF_ADDR (DSP2_SW_DMA_READER_DRAM_BASE * BYTES_IN_MIU_LINE)
180 #define SW_DMA_RDR1_BUF_SIZE ((DSP2_SW_DMA_READER_DRAM_SIZE + 1) * BYTES_IN_MIU_LINE)
195 #define PCM_CAPTURE1_BUF_ADDR (DSP2_PCM_CAPTURE_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
196 #define PCM_CAPTURE1_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
201 #define PCM_CAPTURE2_BUF_ADDR (DSP2_PCM_CAPTURE2_BUFFER_DRAM_BASE * BYTES_IN_MIU_LINE)
202 #define PCM_CAPTURE2_BUF_SIZE (DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE * BYTES_IN_MIU_LINE)
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