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Searched refs:BIT_ (Results 1 – 25 of 69) sorted by relevance

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/utopia/UTPA2-700.0.x/mxlib/include/
H A DdrvAVD.h188 #define VD_SYNC_LOCKED ((BIT_(15)))
189 #define VD_HSYNC_LOCKED ((BIT_(14)))
190 #define VD_INTERLACED ((BIT_(13)))
191 #define VD_VSYNC_50HZ ((BIT_(12)))
192 #define VD_RESET_ON ((BIT_(11)))
193 #define VD_COLOR_LOCKED ((BIT_(10)))
194 #define VD_PAL_SWITCH ((BIT_(9)))
195 #define VD_FSC_TYPE ((BIT_(7))|(BIT_(6))|(BIT_(5)))
196 #define VD_FSC_3579 ((BIT_(6))) // NTSC
197 #define VD_FSC_3575 ((BIT_(7))) // PAL(M)
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H A DdrvPWS.h203 _USB_ = BIT_(0),
204 _SV_ = BIT_(1),
205 _HDMI4_ = BIT_(2),
206 _HDMI3_ = BIT_(3),
207 _HDMI2_ = BIT_(4),
208 _HDMI1_ = BIT_(5),
209 _YPbPr_ = BIT_(6),
210 _SCART_ = BIT_(7),
211 _RGB_ = BIT_(8),
212 _CVBS_ = BIT_(9),
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/utopia/UTPA2-700.0.x/projects/tmplib/include/
H A DdrvAVD.h188 #define VD_SYNC_LOCKED ((BIT_(15)))
189 #define VD_HSYNC_LOCKED ((BIT_(14)))
190 #define VD_INTERLACED ((BIT_(13)))
191 #define VD_VSYNC_50HZ ((BIT_(12)))
192 #define VD_RESET_ON ((BIT_(11)))
193 #define VD_COLOR_LOCKED ((BIT_(10)))
194 #define VD_PAL_SWITCH ((BIT_(9)))
195 #define VD_FSC_TYPE ((BIT_(7))|(BIT_(6))|(BIT_(5)))
196 #define VD_FSC_3579 ((BIT_(6))) // NTSC
197 #define VD_FSC_3575 ((BIT_(7))) // PAL(M)
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H A DdrvPWS.h203 _USB_ = BIT_(0),
204 _SV_ = BIT_(1),
205 _HDMI4_ = BIT_(2),
206 _HDMI3_ = BIT_(3),
207 _HDMI2_ = BIT_(4),
208 _HDMI1_ = BIT_(5),
209 _YPbPr_ = BIT_(6),
210 _SCART_ = BIT_(7),
211 _RGB_ = BIT_(8),
212 _CVBS_ = BIT_(9),
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H A DdrvDMD_ATSC.h205 #ifndef BIT_
206 #define BIT_(n) (1 << (n)) macro
209 #define DMD_ATSC_LOCK_VSB_PRE_LOCK BIT_(0)
210 #define DMD_ATSC_LOCK_VSB_FSYNC_LOCK BIT_(1)
211 #define DMD_ATSC_LOCK_VSB_CE_LOCK BIT_(2)
212 #define DMD_ATSC_LOCK_VSB_FEC_LOCK BIT_(3)
214 #define DMD_ATSC_LOCK_QAM_AGC_LOCK BIT_(8)
215 #define DMD_ATSC_LOCK_QAM_PRE_LOCK BIT_(9)
216 #define DMD_ATSC_LOCK_QAM_MAIN_LOCK BIT_(10)
/utopia/UTPA2-700.0.x/modules/vd/drv/avd/
H A DdrvAVD_v2.h137 #define VD_SYNC_LOCKED ((BIT_(15)))
138 #define VD_HSYNC_LOCKED ((BIT_(14)))
139 #define VD_INTERLACED ((BIT_(13)))
140 #define VD_VSYNC_50HZ ((BIT_(12)))
141 #define VD_RESET_ON ((BIT_(11)))
142 #define VD_COLOR_LOCKED ((BIT_(10)))
143 #define VD_PAL_SWITCH ((BIT_(9)))
144 #define VD_FSC_TYPE ((BIT_(7))|(BIT_(6))|(BIT_(5)))
145 #define VD_FSC_3579 ((BIT_(6))) // NTSC
146 #define VD_FSC_3575 ((BIT_(7))) // PAL(M)
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/macan/demod/
H A DhalDMD_INTERN_common.c703 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3)); in HAL_DMD_TS1_Tristate()
718 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
723 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
739 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
743 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
760 …*fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x1… in HAL_DMD_TS_GetClockRate()
805 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
806 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
811 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
812 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/messi/demod/
H A DhalDMD_INTERN_common.c703 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3)); in HAL_DMD_TS1_Tristate()
718 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
723 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
739 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
743 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
760 …*fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x1… in HAL_DMD_TS_GetClockRate()
805 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
806 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
811 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
812 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/mainz/demod/
H A DhalDMD_INTERN_common.c703 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3)); in HAL_DMD_TS1_Tristate()
718 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
723 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
739 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
743 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
760 …*fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x1… in HAL_DMD_TS_GetClockRate()
805 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
806 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
811 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
812 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/maldives/demod/
H A DhalDMD_INTERN_common.c703 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3)); in HAL_DMD_TS1_Tristate()
718 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
723 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
739 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
743 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
760 …*fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x1… in HAL_DMD_TS_GetClockRate()
805 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
806 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
811 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
812 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/mustang/demod/
H A DhalDMD_INTERN_common.c703 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3)); in HAL_DMD_TS1_Tristate()
718 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
723 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
739 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
743 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
760 …*fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x1… in HAL_DMD_TS_GetClockRate()
805 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
806 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
811 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
812 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/mooney/demod/
H A DhalDMD_INTERN_common.c703 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3)); in HAL_DMD_TS1_Tristate()
718 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
723 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
739 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
743 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
760 …*fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x1… in HAL_DMD_TS_GetClockRate()
805 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
806 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
811 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
812 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7621/demod/
H A DhalDMD_INTERN_common.c765 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3)); in HAL_DMD_TS1_Tristate()
780 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
785 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
801 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
805 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
823 …*fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x1… in HAL_DMD_TS_GetClockRate()
868 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
869 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
874 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
875 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/manhattan/demod/
H A DhalDMD_INTERN_common.c764 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3)); in HAL_DMD_TS1_Tristate()
779 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
784 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
800 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
804 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
822 …*fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x1… in HAL_DMD_TS_GetClockRate()
867 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
868 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
873 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
874 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6lite/demod/
H A DhalDMD_INTERN_common.c765 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3)); in HAL_DMD_TS1_Tristate()
780 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
785 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
801 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
805 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
823 …*fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x1… in HAL_DMD_TS_GetClockRate()
868 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
869 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
874 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
875 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
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/utopia/UTPA2-700.0.x/modules/demodulator/hal/k6/demod/
H A DhalDMD_INTERN_common.c765 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3)); in HAL_DMD_TS1_Tristate()
780 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
785 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
801 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
805 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
823 …*fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x1… in HAL_DMD_TS_GetClockRate()
868 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
869 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
874 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
875 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maxim/demod/
H A DhalDMD_INTERN_common.c766 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3)); in HAL_DMD_TS1_Tristate()
781 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
786 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
802 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
806 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
824 …*fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x1… in HAL_DMD_TS_GetClockRate()
869 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
870 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
875 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
876 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/maserati/demod/
H A DhalDMD_INTERN_common.c765 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3)); in HAL_DMD_TS1_Tristate()
780 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
785 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
801 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
805 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
823 …*fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x1… in HAL_DMD_TS_GetClockRate()
868 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
869 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
874 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
875 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/curry/demod/
H A DhalDMD_INTERN_common.c765 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3)); in HAL_DMD_TS1_Tristate()
780 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
785 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
801 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
805 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
823 …*fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x1… in HAL_DMD_TS_GetClockRate()
868 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
869 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
874 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
875 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/M7821/demod/
H A DhalDMD_INTERN_common.c765 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3)); in HAL_DMD_TS1_Tristate()
780 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
785 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
801 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
805 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
823 …*fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x1… in HAL_DMD_TS_GetClockRate()
868 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
869 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
874 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
875 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
[all …]
/utopia/UTPA2-700.0.x/modules/demodulator/hal/kano/demod/
H A DhalDMD_INTERN_common.c765 HAL_DMD_RIU_WriteByteMask(0x101EAF, (BIT_(5))|(BIT_(4))|(BIT_(3)), BMASK(5:3)); in HAL_DMD_TS1_Tristate()
780 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
785 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(0)), (BIT_(0))); in HAL_DMD_RFAGC_Tristate()
801 HAL_DMD_RIU_WriteByteMask(0x11286C, 0, (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
805 HAL_DMD_RIU_WriteByteMask(0x11286C, (BIT_(4)), (BIT_(4))); in HAL_DMD_IFAGC_Tristate()
823 …*fTS_CLK=(HAL_DMD_RIU_ReadRegBit(0x103301, BIT_(0)) ? 288.0 : 348.0)/(2*((HAL_DMD_RIU_ReadByte(0x1… in HAL_DMD_TS_GetClockRate()
868 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(5)); // enable SIF PGA in HAL_DMD_SIF_PGA_Ctl()
869 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(2)); // disable IMUX clamping in HAL_DMD_SIF_PGA_Ctl()
874 HAL_DMD_RIU_WriteRegBit(0x112840, bPGAEnable, BIT_(6)); // enable VIF PGA in HAL_DMD_VIF_PGA_Ctl()
875 HAL_DMD_RIU_WriteRegBit(0x112802, bPGAEnable, BIT_(3)); // disable IMUX clamping in HAL_DMD_VIF_PGA_Ctl()
[all …]
/utopia/UTPA2-700.0.x/modules/sys/hal/maxim/sys/
H A DhalDMD_VD_MBX.h128 #define BIN_FOR_ATV BIT_(0)
129 #define BIN_FOR_DVBT BIT_(1)
130 #define BIN_FOR_DVBC BIT_(2)
131 #define BIN_FOR_ATSC BIT_(3)
132 #define BIN_FOR_ISDBT BIT_(4)
133 #define BIN_FOR_DTMB BIT_(5)
134 #define BIN_FOR_DVBS BIT_(6)
135 #define BIN_FOR_DVBT2 BIT_(7)
/utopia/UTPA2-700.0.x/modules/sys/hal/k6lite/sys/
H A DhalDMD_VD_MBX.h128 #define BIN_FOR_ATV BIT_(0)
129 #define BIN_FOR_DVBT BIT_(1)
130 #define BIN_FOR_DVBC BIT_(2)
131 #define BIN_FOR_ATSC BIT_(3)
132 #define BIN_FOR_ISDBT BIT_(4)
133 #define BIN_FOR_DTMB BIT_(5)
134 #define BIN_FOR_DVBS BIT_(6)
135 #define BIN_FOR_DVBT2 BIT_(7)
/utopia/UTPA2-700.0.x/modules/sys/hal/mustang/sys/
H A DhalDMD_VD_MBX.h112 #define BIN_FOR_ATV BIT_(0)
113 #define BIN_FOR_DVBT BIT_(1)
114 #define BIN_FOR_DVBC BIT_(2)
115 #define BIN_FOR_ATSC BIT_(3)
116 #define BIN_FOR_ISDBT BIT_(4)
117 #define BIN_FOR_DTMB BIT_(5)
118 #define BIN_FOR_DVBS BIT_(6)
119 #define BIN_FOR_DVBT2 BIT_(7)
/utopia/UTPA2-700.0.x/modules/sys/hal/maserati/sys/
H A DhalDMD_VD_MBX.h128 #define BIN_FOR_ATV BIT_(0)
129 #define BIN_FOR_DVBT BIT_(1)
130 #define BIN_FOR_DVBC BIT_(2)
131 #define BIN_FOR_ATSC BIT_(3)
132 #define BIN_FOR_ISDBT BIT_(4)
133 #define BIN_FOR_DTMB BIT_(5)
134 #define BIN_FOR_DVBS BIT_(6)
135 #define BIN_FOR_DVBT2 BIT_(7)

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