| /utopia/UTPA2-700.0.x/modules/gpio/hal/maldives/gpio/ |
| H A D | halGPIO.c | 108 #define BIT3 BIT(3) macro
273 #define GPIO29_OEN 0x0e4e, BIT3
275 #define GPIO29_IN 0x0e4f, BIT3
333 #define GPIO41_OEN 0x1423, BIT3
334 #define GPIO41_OUT 0x1424, BIT3
335 #define GPIO41_IN 0x1425, BIT3
373 #define GPIO49_OEN 0x101e5C, BIT3
374 #define GPIO49_OUT 0x101e56, BIT3
375 #define GPIO49_IN 0x101e50, BIT3
413 #define GPIO57_OEN 0x101e5D, BIT3
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| /utopia/UTPA2-700.0.x/modules/gpio/hal/mustang/gpio/ |
| H A D | halGPIO.c | 108 #define BIT3 BIT(3) macro
273 #define GPIO29_OEN 0x0e4e, BIT3
275 #define GPIO29_IN 0x0e4f, BIT3
333 #define GPIO41_OEN 0x1423, BIT3
334 #define GPIO41_OUT 0x1424, BIT3
335 #define GPIO41_IN 0x1425, BIT3
388 #define GPIO52_OEN 0x101e5C, BIT3
389 #define GPIO52_OUT 0x101e56, BIT3
390 #define GPIO52_IN 0x101e50, BIT3
428 #define GPIO60_OEN 0x101e5D, BIT3
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/k7u/mvop/ |
| H A D | regMVOP.h | 162 #define VOP_DMA_THD (BIT0|BIT1|BIT2|BIT3|BIT4)
181 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
193 #define VOP_SRAM_SD_MASK BIT3
205 #define VOP_YUV_STR_HIBITS (BIT4 | BIT3 | BIT2 |BIT1 | BIT0) //Bits(28:24)
225 #define VOP_HVD_EN BIT3
262 #define VOP_GCLK_VCLK_ON BIT3 //clk_dc0 use 0: free-run clock; 1: gated clock
273 #define VOP_FD_MASK_INV BIT3
293 #define VOP_INFO_FROM_CODEC_PROG_SEQ (BIT3) //progressive sequence
323 #define VOP_FIELD_FROM_ADDR (BIT3) //decide top or bot by diu addr
326 #define VOP_MIRROR_CFG_ENABLE (BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
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| /utopia/UTPA2-700.0.x/modules/pws/hal/maldives/pws/ |
| H A D | regCLKGEN.h | 105 #define CKG_DOT_MINI_MASK (BIT3 | BIT2)
126 #define CKG_TS0_MASK (BIT3 | BIT2)
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
170 #define CKG_MVD_BOOT_MASK (BIT3 | BIT2)
188 #define CKG_MVD_IAP_RMEM_MASK (BIT3 | BIT2)
211 #define CKG_RVD_MASK (BIT3 | BIT2)
229 #define CKG_GOPG0_MASK (BIT3 | BIT2)
247 #define CKG_GOPD_MASK (BIT3 | BIT2)
265 #define CKG_VDMCU_MASK (BIT3 | BIT2)
292 #define CKG_GOPG2_MASK (BIT3 | BIT2)
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| /utopia/UTPA2-700.0.x/modules/pws/hal/k6/pws/ |
| H A D | regCLKGEN.h | 105 #define CKG_DOT_MINI_MASK (BIT3 | BIT2)
126 #define CKG_TS0_MASK (BIT3 | BIT2)
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
170 #define CKG_MVD_BOOT_MASK (BIT3 | BIT2)
188 #define CKG_MVD_IAP_RMEM_MASK (BIT3 | BIT2)
211 #define CKG_RVD_MASK (BIT3 | BIT2)
229 #define CKG_GOPG0_MASK (BIT3 | BIT2)
247 #define CKG_GOPD_MASK (BIT3 | BIT2)
265 #define CKG_VDMCU_MASK (BIT3 | BIT2)
292 #define CKG_GOPG2_MASK (BIT3 | BIT2)
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| /utopia/UTPA2-700.0.x/modules/pws/hal/macan/pws/ |
| H A D | regCLKGEN.h | 105 #define CKG_DOT_MINI_MASK (BIT3 | BIT2)
126 #define CKG_TS0_MASK (BIT3 | BIT2)
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
170 #define CKG_MVD_BOOT_MASK (BIT3 | BIT2)
188 #define CKG_MVD_IAP_RMEM_MASK (BIT3 | BIT2)
211 #define CKG_RVD_MASK (BIT3 | BIT2)
229 #define CKG_GOPG0_MASK (BIT3 | BIT2)
247 #define CKG_GOPD_MASK (BIT3 | BIT2)
265 #define CKG_VDMCU_MASK (BIT3 | BIT2)
292 #define CKG_GOPG2_MASK (BIT3 | BIT2)
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| /utopia/UTPA2-700.0.x/modules/pws/hal/mooney/pws/ |
| H A D | regCLKGEN.h | 105 #define CKG_DOT_MINI_MASK (BIT3 | BIT2)
126 #define CKG_TS0_MASK (BIT3 | BIT2)
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
170 #define CKG_MVD_BOOT_MASK (BIT3 | BIT2)
188 #define CKG_MVD_IAP_RMEM_MASK (BIT3 | BIT2)
211 #define CKG_RVD_MASK (BIT3 | BIT2)
229 #define CKG_GOPG0_MASK (BIT3 | BIT2)
247 #define CKG_GOPD_MASK (BIT3 | BIT2)
265 #define CKG_VDMCU_MASK (BIT3 | BIT2)
292 #define CKG_GOPG2_MASK (BIT3 | BIT2)
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| /utopia/UTPA2-700.0.x/modules/pws/hal/messi/pws/ |
| H A D | regCLKGEN.h | 105 #define CKG_DOT_MINI_MASK (BIT3 | BIT2)
126 #define CKG_TS0_MASK (BIT3 | BIT2)
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
170 #define CKG_MVD_BOOT_MASK (BIT3 | BIT2)
188 #define CKG_MVD_IAP_RMEM_MASK (BIT3 | BIT2)
211 #define CKG_RVD_MASK (BIT3 | BIT2)
229 #define CKG_GOPG0_MASK (BIT3 | BIT2)
247 #define CKG_GOPD_MASK (BIT3 | BIT2)
265 #define CKG_VDMCU_MASK (BIT3 | BIT2)
292 #define CKG_GOPG2_MASK (BIT3 | BIT2)
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| /utopia/UTPA2-700.0.x/modules/pws/hal/manhattan/pws/ |
| H A D | regCLKGEN.h | 105 #define CKG_DOT_MINI_MASK (BIT3 | BIT2)
126 #define CKG_TS0_MASK (BIT3 | BIT2)
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
170 #define CKG_MVD_BOOT_MASK (BIT3 | BIT2)
188 #define CKG_MVD_IAP_RMEM_MASK (BIT3 | BIT2)
211 #define CKG_RVD_MASK (BIT3 | BIT2)
229 #define CKG_GOPG0_MASK (BIT3 | BIT2)
247 #define CKG_GOPD_MASK (BIT3 | BIT2)
265 #define CKG_VDMCU_MASK (BIT3 | BIT2)
292 #define CKG_GOPG2_MASK (BIT3 | BIT2)
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| /utopia/UTPA2-700.0.x/modules/pws/hal/k6lite/pws/ |
| H A D | regCLKGEN.h | 105 #define CKG_DOT_MINI_MASK (BIT3 | BIT2)
126 #define CKG_TS0_MASK (BIT3 | BIT2)
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
170 #define CKG_MVD_BOOT_MASK (BIT3 | BIT2)
188 #define CKG_MVD_IAP_RMEM_MASK (BIT3 | BIT2)
211 #define CKG_RVD_MASK (BIT3 | BIT2)
229 #define CKG_GOPG0_MASK (BIT3 | BIT2)
247 #define CKG_GOPD_MASK (BIT3 | BIT2)
265 #define CKG_VDMCU_MASK (BIT3 | BIT2)
292 #define CKG_GOPG2_MASK (BIT3 | BIT2)
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| /utopia/UTPA2-700.0.x/modules/pws/hal/M7821/pws/ |
| H A D | regCLKGEN.h | 105 #define CKG_DOT_MINI_MASK (BIT3 | BIT2)
126 #define CKG_TS0_MASK (BIT3 | BIT2)
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
170 #define CKG_MVD_BOOT_MASK (BIT3 | BIT2)
188 #define CKG_MVD_IAP_RMEM_MASK (BIT3 | BIT2)
211 #define CKG_RVD_MASK (BIT3 | BIT2)
229 #define CKG_GOPG0_MASK (BIT3 | BIT2)
247 #define CKG_GOPD_MASK (BIT3 | BIT2)
265 #define CKG_VDMCU_MASK (BIT3 | BIT2)
292 #define CKG_GOPG2_MASK (BIT3 | BIT2)
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| /utopia/UTPA2-700.0.x/modules/pws/hal/mainz/pws/ |
| H A D | regCLKGEN.h | 105 #define CKG_DOT_MINI_MASK (BIT3 | BIT2)
126 #define CKG_TS0_MASK (BIT3 | BIT2)
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
170 #define CKG_MVD_BOOT_MASK (BIT3 | BIT2)
188 #define CKG_MVD_IAP_RMEM_MASK (BIT3 | BIT2)
211 #define CKG_RVD_MASK (BIT3 | BIT2)
229 #define CKG_GOPG0_MASK (BIT3 | BIT2)
247 #define CKG_GOPD_MASK (BIT3 | BIT2)
265 #define CKG_VDMCU_MASK (BIT3 | BIT2)
292 #define CKG_GOPG2_MASK (BIT3 | BIT2)
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| /utopia/UTPA2-700.0.x/modules/pws/hal/mustang/pws/ |
| H A D | regCLKGEN.h | 105 #define CKG_DOT_MINI_MASK (BIT3 | BIT2)
126 #define CKG_TS0_MASK (BIT3 | BIT2)
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
170 #define CKG_MVD_BOOT_MASK (BIT3 | BIT2)
188 #define CKG_MVD_IAP_RMEM_MASK (BIT3 | BIT2)
211 #define CKG_RVD_MASK (BIT3 | BIT2)
229 #define CKG_GOPG0_MASK (BIT3 | BIT2)
247 #define CKG_GOPD_MASK (BIT3 | BIT2)
265 #define CKG_VDMCU_MASK (BIT3 | BIT2)
292 #define CKG_GOPG2_MASK (BIT3 | BIT2)
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| /utopia/UTPA2-700.0.x/modules/pws/hal/maxim/pws/ |
| H A D | regCLKGEN.h | 105 #define CKG_DOT_MINI_MASK (BIT3 | BIT2)
126 #define CKG_TS0_MASK (BIT3 | BIT2)
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
170 #define CKG_MVD_BOOT_MASK (BIT3 | BIT2)
188 #define CKG_MVD_IAP_RMEM_MASK (BIT3 | BIT2)
211 #define CKG_RVD_MASK (BIT3 | BIT2)
229 #define CKG_GOPG0_MASK (BIT3 | BIT2)
247 #define CKG_GOPD_MASK (BIT3 | BIT2)
265 #define CKG_VDMCU_MASK (BIT3 | BIT2)
292 #define CKG_GOPG2_MASK (BIT3 | BIT2)
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| /utopia/UTPA2-700.0.x/modules/pws/hal/M7621/pws/ |
| H A D | regCLKGEN.h | 105 #define CKG_DOT_MINI_MASK (BIT3 | BIT2)
126 #define CKG_TS0_MASK (BIT3 | BIT2)
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
170 #define CKG_MVD_BOOT_MASK (BIT3 | BIT2)
188 #define CKG_MVD_IAP_RMEM_MASK (BIT3 | BIT2)
211 #define CKG_RVD_MASK (BIT3 | BIT2)
229 #define CKG_GOPG0_MASK (BIT3 | BIT2)
247 #define CKG_GOPD_MASK (BIT3 | BIT2)
265 #define CKG_VDMCU_MASK (BIT3 | BIT2)
292 #define CKG_GOPG2_MASK (BIT3 | BIT2)
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| /utopia/UTPA2-700.0.x/modules/pws/hal/curry/pws/ |
| H A D | regCLKGEN.h | 105 #define CKG_DOT_MINI_MASK (BIT3 | BIT2)
126 #define CKG_TS0_MASK (BIT3 | BIT2)
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
170 #define CKG_MVD_BOOT_MASK (BIT3 | BIT2)
188 #define CKG_MVD_IAP_RMEM_MASK (BIT3 | BIT2)
211 #define CKG_RVD_MASK (BIT3 | BIT2)
229 #define CKG_GOPG0_MASK (BIT3 | BIT2)
247 #define CKG_GOPD_MASK (BIT3 | BIT2)
265 #define CKG_VDMCU_MASK (BIT3 | BIT2)
292 #define CKG_GOPG2_MASK (BIT3 | BIT2)
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| /utopia/UTPA2-700.0.x/modules/pws/hal/kano/pws/ |
| H A D | regCLKGEN.h | 105 #define CKG_DOT_MINI_MASK (BIT3 | BIT2)
126 #define CKG_TS0_MASK (BIT3 | BIT2)
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
170 #define CKG_MVD_BOOT_MASK (BIT3 | BIT2)
188 #define CKG_MVD_IAP_RMEM_MASK (BIT3 | BIT2)
211 #define CKG_RVD_MASK (BIT3 | BIT2)
229 #define CKG_GOPG0_MASK (BIT3 | BIT2)
247 #define CKG_GOPD_MASK (BIT3 | BIT2)
265 #define CKG_VDMCU_MASK (BIT3 | BIT2)
292 #define CKG_GOPG2_MASK (BIT3 | BIT2)
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| /utopia/UTPA2-700.0.x/modules/pws/hal/maserati/pws/ |
| H A D | regCLKGEN.h | 105 #define CKG_DOT_MINI_MASK (BIT3 | BIT2)
126 #define CKG_TS0_MASK (BIT3 | BIT2)
143 #define CKG_TSP_MASK (BIT4 | BIT3 | BIT2)
170 #define CKG_MVD_BOOT_MASK (BIT3 | BIT2)
188 #define CKG_MVD_IAP_RMEM_MASK (BIT3 | BIT2)
211 #define CKG_RVD_MASK (BIT3 | BIT2)
229 #define CKG_GOPG0_MASK (BIT3 | BIT2)
247 #define CKG_GOPD_MASK (BIT3 | BIT2)
265 #define CKG_VDMCU_MASK (BIT3 | BIT2)
292 #define CKG_GOPG2_MASK (BIT3 | BIT2)
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/k6/mvop/ |
| H A D | regMVOP.h | 161 #define VOP_DMA_THD (BIT0|BIT1|BIT2|BIT3|BIT4)
180 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
188 #define VOP_SRAM_SD_MASK BIT3
200 #define VOP_YUV_STR_HIBITS (BIT4 | BIT3 | BIT2 |BIT1 | BIT0) //Bits(28:24)
220 #define VOP_HVD_EN BIT3
257 #define VOP_GCLK_VCLK_ON BIT3 //clk_dc0 use 0: free-run clock; 1: gated clock
268 #define VOP_FD_MASK_INV BIT3
288 #define VOP_INFO_FROM_CODEC_PROG_SEQ (BIT3) //progressive sequence
318 #define VOP_FIELD_FROM_ADDR (BIT3) //decide top or bot by diu addr
321 #define VOP_MIRROR_CFG_ENABLE (BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/k6lite/mvop/ |
| H A D | regMVOP.h | 161 #define VOP_DMA_THD (BIT0|BIT1|BIT2|BIT3|BIT4)
180 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
188 #define VOP_SRAM_SD_MASK BIT3
200 #define VOP_YUV_STR_HIBITS (BIT4 | BIT3 | BIT2 |BIT1 | BIT0) //Bits(28:24)
220 #define VOP_HVD_EN BIT3
257 #define VOP_GCLK_VCLK_ON BIT3 //clk_dc0 use 0: free-run clock; 1: gated clock
268 #define VOP_FD_MASK_INV BIT3
288 #define VOP_INFO_FROM_CODEC_PROG_SEQ (BIT3) //progressive sequence
318 #define VOP_FIELD_FROM_ADDR (BIT3) //decide top or bot by diu addr
321 #define VOP_MIRROR_CFG_ENABLE (BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
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| /utopia/UTPA2-700.0.x/modules/sar/hal/k6/sar/ |
| H A D | regSAR.h | 108 …#define _SAR_LEVEL_TRIGGER (BIT3) //keypad level trigger enable. 0: use edge tri…
118 #define _SAR_NCH_EN (BIT3)
157 #define _SAR_AISEL (BIT4|BIT3|BIT2|BIT1|BIT0)
161 #define _SAR_AISEL_CH4 (BIT3)
165 #define _SAR_OEN_GPIO_MSK (BIT4|BIT3|BIT2|BIT1|BIT0)
169 #define _SAR_OEN_GPIO_CH4 (BIT3)
173 #define _SAR_I_GPIO_MSK (BIT4|BIT3|BIT2|BIT1|BIT0)
177 #define _SAR_I_GPIO_CH4 (BIT3)
181 #define _SAR_C_GPIO_MSK (BIT4|BIT3|BIT2|BIT1|BIT0)
185 #define _SAR_C_GPIO_CH4 (BIT3)
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| /utopia/UTPA2-700.0.x/modules/sar/hal/kano/sar/ |
| H A D | regSAR.h | 108 …#define _SAR_LEVEL_TRIGGER (BIT3) //keypad level trigger enable. 0: use edge tri…
118 #define _SAR_NCH_EN (BIT3)
157 #define _SAR_AISEL (BIT4|BIT3|BIT2|BIT1|BIT0)
161 #define _SAR_AISEL_CH4 (BIT3)
165 #define _SAR_OEN_GPIO_MSK (BIT4|BIT3|BIT2|BIT1|BIT0)
169 #define _SAR_OEN_GPIO_CH4 (BIT3)
173 #define _SAR_I_GPIO_MSK (BIT4|BIT3|BIT2|BIT1|BIT0)
177 #define _SAR_I_GPIO_CH4 (BIT3)
181 #define _SAR_C_GPIO_MSK (BIT4|BIT3|BIT2|BIT1|BIT0)
185 #define _SAR_C_GPIO_CH4 (BIT3)
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| /utopia/UTPA2-700.0.x/modules/sar/hal/k6lite/sar/ |
| H A D | regSAR.h | 108 …#define _SAR_LEVEL_TRIGGER (BIT3) //keypad level trigger enable. 0: use edge tri…
118 #define _SAR_NCH_EN (BIT3)
157 #define _SAR_AISEL (BIT4|BIT3|BIT2|BIT1|BIT0)
161 #define _SAR_AISEL_CH4 (BIT3)
165 #define _SAR_OEN_GPIO_MSK (BIT4|BIT3|BIT2|BIT1|BIT0)
169 #define _SAR_OEN_GPIO_CH4 (BIT3)
173 #define _SAR_I_GPIO_MSK (BIT4|BIT3|BIT2|BIT1|BIT0)
177 #define _SAR_I_GPIO_CH4 (BIT3)
181 #define _SAR_C_GPIO_MSK (BIT4|BIT3|BIT2|BIT1|BIT0)
185 #define _SAR_C_GPIO_CH4 (BIT3)
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/kastor/mvop/ |
| H A D | regMVOP.h | 160 #define VOP_DMA_THD (BIT0|BIT1|BIT2|BIT3|BIT4)
179 #define VOP_HI_TSH (BIT3|BIT4|BIT5|BIT6) //DMA High priority threshold
187 #define VOP_SRAM_SD_MASK BIT3
198 #define VOP_YUV_STR_HIBITS (BIT4 | BIT3 | BIT2 |BIT1 | BIT0) //Bits(28:24)
217 #define VOP_HVD_EN BIT3
254 #define VOP_GCLK_VCLK_ON BIT3 //clk_dc0 use 0: free-run clock; 1: gated clock
265 #define VOP_FD_MASK_INV BIT3
285 #define VOP_INFO_FROM_CODEC_PROG_SEQ (BIT3) //progressive sequence
315 #define VOP_FIELD_FROM_ADDR (BIT3) //decide top or bot by diu addr
318 #define VOP_MIRROR_CFG_ENABLE (BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
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| /utopia/UTPA2-700.0.x/modules/sar/hal/maldives/sar/ |
| H A D | regSAR.h | 108 …#define _SAR_LEVEL_TRIGGER (BIT3) //keypad level trigger enable. 0: use edge tri…
118 #define _SAR_NCH_EN (BIT3)
155 #define _SAR_AISEL (BIT4|BIT3|BIT2|BIT1|BIT0)
159 #define _SAR_AISEL_CH4 (BIT3)
163 #define _SAR_OEN_GPIO_MSK (BIT4|BIT3|BIT2|BIT1|BIT0)
167 #define _SAR_OEN_GPIO_CH4 (BIT3)
171 #define _SAR_I_GPIO_MSK (BIT4|BIT3|BIT2|BIT1|BIT0)
175 #define _SAR_I_GPIO_CH4 (BIT3)
179 #define _SAR_C_GPIO_MSK (BIT4|BIT3|BIT2|BIT1|BIT0)
183 #define _SAR_C_GPIO_CH4 (BIT3)
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