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Searched refs:SwReg05 (Results 1 – 6 of 6) sorted by relevance

/rockchip-linux_mpp/mpp/hal/vpu/mpg4d/
H A Dhal_m4vd_vdpu1.c106 regs->SwReg05.sw_intradc_vlc_thr = pp->intra_dc_vlc_thr; in vdpu1_mpg4d_setup_regs_by_syntax()
108 regs->SwReg05.sw_sync_markers_e = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
126 regs->SwReg05.sw_strm_start_bit = start_bit_offset; in vdpu1_mpg4d_setup_regs_by_syntax()
129 regs->SwReg05.sw_vop_time_incr = pp->vop_time_increment_resolution; in vdpu1_mpg4d_setup_regs_by_syntax()
219 regs->SwReg05.sw_type1_quant_e = pp->quant_type; in vdpu1_mpg4d_setup_regs_by_syntax()
H A Dhal_m4vd_vdpu1_reg.h108 } SwReg05; member
/rockchip-linux_mpp/mpp/hal/vpu/h263d/
H A Dhal_h263d_vdpu1.c70 regs->SwReg05.sw_sync_markers_e = 1; in vpu1_h263d_setup_regs_by_syntax()
88 regs->SwReg05.sw_strm_start_bit = start_bit_offset; in vpu1_h263d_setup_regs_by_syntax()
92 regs->SwReg05.sw_vop_time_incr = pp->vop_time_increment_resolution; in vpu1_h263d_setup_regs_by_syntax()
H A Dhal_h263d_vdpu1_reg.h107 } SwReg05; member
/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu1.c457 p_regs->SwReg05.sw_strm_start_bit = 0; /* sodb stream start bit */ in vdpu1_set_vlc_regs()
610 p_regs->SwReg05.sw_ch_qp_offset = pp->chroma_qp_index_offset; in vdpu1_set_asic_regs()
611 p_regs->SwReg05.sw_ch_qp_offset2 = pp->second_chroma_qp_index_offset; in vdpu1_set_asic_regs()
637 p_regs->SwReg05.sw_fieldpic_flag_e = (!pp->frame_mbs_only_flag) ? 1 : 0; in vdpu1_set_asic_regs()
648 p_regs->SwReg05.sw_type1_quant_e = pp->scaleing_list_enable_flag; in vdpu1_set_asic_regs()
H A Dhal_h264d_vdpu1_reg.h108 } SwReg05; member