Searched refs:pdiv2 (Results 1 – 3 of 3) sorted by relevance
37 u32 pdiv2; member
96 rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV2_REG, data->pdiv2); in setup_clock_synthesizer()
605 .pdiv2 = 0x2,674 cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */ in board_init()