1*3164f3c6SLokesh Vutla /* 2*3164f3c6SLokesh Vutla * clk-synthesizer.h 3*3164f3c6SLokesh Vutla * 4*3164f3c6SLokesh Vutla * Clock synthesizer header 5*3164f3c6SLokesh Vutla * 6*3164f3c6SLokesh Vutla * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/ 7*3164f3c6SLokesh Vutla * 8*3164f3c6SLokesh Vutla * SPDX-License-Identifier: GPL-2.0+ 9*3164f3c6SLokesh Vutla */ 10*3164f3c6SLokesh Vutla 11*3164f3c6SLokesh Vutla #ifndef __CLK_SYNTHESIZER_H 12*3164f3c6SLokesh Vutla #define __CLK_SYNTHESIZER_H 13*3164f3c6SLokesh Vutla 14*3164f3c6SLokesh Vutla #include <common.h> 15*3164f3c6SLokesh Vutla 16*3164f3c6SLokesh Vutla #define CLK_SYNTHESIZER_ID_REG 0x0 17*3164f3c6SLokesh Vutla #define CLK_SYNTHESIZER_XCSEL 0x05 18*3164f3c6SLokesh Vutla #define CLK_SYNTHESIZER_MUX_REG 0x14 19*3164f3c6SLokesh Vutla #define CLK_SYNTHESIZER_PDIV2_REG 0x16 20*3164f3c6SLokesh Vutla #define CLK_SYNTHESIZER_PDIV3_REG 0x17 21*3164f3c6SLokesh Vutla 22*3164f3c6SLokesh Vutla #define CLK_SYNTHESIZER_BYTE_MODE 0x80 23*3164f3c6SLokesh Vutla 24*3164f3c6SLokesh Vutla /** 25*3164f3c6SLokesh Vutla * struct clk_synth: This structure holds data neeed for configuring 26*3164f3c6SLokesh Vutla * for clock synthesizer. 27*3164f3c6SLokesh Vutla * @id: The id of synthesizer 28*3164f3c6SLokesh Vutla * @capacitor: value of the capacitor attached 29*3164f3c6SLokesh Vutla * @mux: mux settings. 30*3164f3c6SLokesh Vutla * @pdiv2: Div to be applied to second output 31*3164f3c6SLokesh Vutla * @pdiv3: Div to be applied to third output 32*3164f3c6SLokesh Vutla */ 33*3164f3c6SLokesh Vutla struct clk_synth { 34*3164f3c6SLokesh Vutla u32 id; 35*3164f3c6SLokesh Vutla u32 capacitor; 36*3164f3c6SLokesh Vutla u32 mux; 37*3164f3c6SLokesh Vutla u32 pdiv2; 38*3164f3c6SLokesh Vutla u32 pdiv3; 39*3164f3c6SLokesh Vutla }; 40*3164f3c6SLokesh Vutla 41*3164f3c6SLokesh Vutla int setup_clock_synthesizer(struct clk_synth *data); 42*3164f3c6SLokesh Vutla 43*3164f3c6SLokesh Vutla #endif 44